Design techniques for high-performance digital PLLs and CDRs Public Deposited

http://ir.library.oregonstate.edu/concern/graduate_thesis_or_dissertations/b8515r017

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  • Phase-Locked Loops (PLLs) are essential building blocks in many communication systems. Designing high performance analog PLLs in the presence of technology imposed constraints such as leakage, poor analog transistor behavior, process variability, and low supply voltage is a challenging task. To overcome these drawbacks, digital PLLs (DPLLs) have recently emerged as an alternative to analog PLLs. In this work, a digital PLL employing a linear proportional path and a double integral path is proposed to achieve low jitter, wide operating range and low power. Moreover, the approach of bandwidth and tuning range tracking is achieved. The prototype DPLL fabricated in a 90nm CMOS process operates from 0.7 to 3.5GHz. At 2.5GHz, the proposed DPLL consumes only 1.6mW power and achieves 1.6ps r.m.s jitter. Moreover, the design techniques for a novel digital clock and data recovery (CDR) with linear loop dynamics are presented. The PLL-based digital CDR avoid the use of TDC, achieves static phase offset free (SPO-free) and well-controlled jitter transfer bandwidth. The prototype digital CDR fabricated in a 0:13μm CMOS process achieves error-free operation (BER < 10⁻¹²) for PRBS data sequences ranging from 2⁷-1 to 2³¹-1 and a near-constant bandwidth of 4.5MHz.
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  • description.provenance : Approved for entry into archive by Laura Wilson(laura.wilson@oregonstate.edu) on 2010-12-01T18:07:36Z (GMT) No. of bitstreams: 1 YinWenjing2011.pdf: 2408661 bytes, checksum: aa9ec914065589f0c1c4d23d6738d697 (MD5)
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