A fast carry binary adder

Graduate Thesis Or Dissertation

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Citeable URL: https://ir.library.oregonstate.edu/concern/graduate_thesis_or_dissertations/b8515r64h

Descriptions

Attribute Name	Values
Creator	Bernhardt, Donn Eugene
Abstract	This thesis describes the adder to be used with the Galaxy computer, which is to be constructed at Oregon State University. The need for faster, more reliable adders is discussed along with previous adder designs related to the Galaxy Fast Carry Adder. Both the logical design and circuit design of the Galaxy Fast Carry Adder are discussed. Operating speed measurements for a 3 bit adder are presented and used to predict operating speeds of a 49 bit adder. Reliability considerations are discussed, and a set of worst case resistor value calculations is included as an appendix. The use of the adder circuit in the Galaxy computer is also discussed.
Resource Type	Masters Thesis
Date Available	2014-06-02T21:51:36+00:00
Date Issued	1963-08-13
Degree Level	Master's
Degree Name	Master of Science (M.S.)
Degree Field	Electrical Engineering
Degree Grantor	Oregon State University
Commencement Year	1964
Advisor	Amort, Donald L.
Academic Affiliation	Electrical Engineering
Non-Academic Affiliation	Oregon State University. Graduate School
Subject	Electronic digital computers -- Design and construction
权利声明	Copyright Not Evaluated
Publisher	Oregon State University
Peer Reviewed	No
Language	English [eng]
Digitization Specifications	File scanned at 300 ppi using Capture Perfect 3.0 on a Canon DR-9050C in PDF format. CVista PdfCompressor 5.0 was used for pdf compression and textual OCR.
Replaces	http://hdl.handle.net/1957/48701

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