Noise optimization for low-voltage CMOS audio preamplifier systems Public Deposited

http://ir.library.oregonstate.edu/concern/graduate_thesis_or_dissertations/bg257h54t

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  • There is a large and growing market for portable consumer audio products with very small size. As the size of these products is reduced, the area occupied by batteries becomes significant and hence limits the number of batteries to one. In order to build such small products, high levels of integration are required to minimize both the number of integrated circuits and off-chip discrete components. With supply voltages limited to that supplied by one battery, special low-voltage and low-power circuit design techniques are required. For digital circuits integrated on a chip, the reduction in supply voltage directly translates to reduced power dissipation. However, for analog circuits on the same chip, the reduction in supply voltage can cause a significant increase in both required power dissipation and die area primarily due to the reduction in available signal swing and the limited selection of suitable low-voltage circuit architectures. The objective of this research was to provide analysis and optimization techniques to meet signal-to-noise ratio specifications with minimum power dissipation and die area. A 0.9V microphone preamplifier and programmable gain amplifier system was designed using these techniques and fabricated with a 0.35um CMOS process.
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