Graduate Thesis Or Dissertation

Analysis and modeling of planar microstrip spiral inductors on lossy substrates

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  • The advent of low-cost RFIC's fabricated in Silicon-based technologies has led to the use of monolithic lumped elements which are located on-die. While it is clearly advantageous to have a high degree of integration and thus fewer off chip elements, parasitic losses due to semiconducting substrate effects can be a performance-limiting factor. Microstrip spiral inductors are key components in many high frequency circuit designs, including MMIC's, RFIC's, and mixed-signal modules. However, the losses associated with spirals fabricated in a lossy substrate environment, such as in CMOS and bipolar technologies, are not accurately modeled by the current conventional techniques. This thesis presents a complete modeling technique for spiral inductors over such 'high-loss' substrates. The quasi-static solution for single and coupled Metal-Insulator-Substrate (MIS) microstrip structures has led to the development of methods for calculating the self and mutual line parameters r, l, g, and c, which are in turn utilized in the model for the microstrip spiral inductors in the same environment. The equivalent circuit model for the spiral inductors is based on the conventional low-loss spiral models with the inclusion of frequency-dependent losses due to semiconducting substrates. The distributed model for spirals in CMOS-based RFICs incorporates inductance calculations by the Partial Element Equivalent Circuit (PEEC) method, augmented by inductance and resistance calculations for the so-called skin effect mode by the spectral domain technique. In addition, the capacitances and shunt conductances can be computed by a Poisson solver for layered lossy media; both network analog and spectral domain methods are also used to find the shunt admittance per unit length for the microstrip structure as a fundamental element of the spiral. Simulations for typical structures have been performed to validate the modeling techniques via comparison with a commercial simulator and network analyzer measurements for a 9.5 turn spiral in CMOS for RFIC applications.
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