Optimum logic design for a fast parallel multiplier

Graduate Thesis Or Dissertation

Public Deposited

Citeable URL: https://ir.library.oregonstate.edu/concern/graduate_thesis_or_dissertations/br86b710x

Descriptions

Attribute Name	Values
Creator	Siemens, Phillip Dennis
Abstract	This thesis discusses a method of fast multiplication by parallel addition of summands. A logical element that performs this parallel addition is defined, and examples of the element realized with threshold logic are shown. Relations between the type of logical element used, and the speed and cost of the multiplier are discussed. The optimum type of logical element is defined, and two examples of a multiplier using this optimum element are discussed. By assuming some hypothetical propagation times for the various elements, a multiply time of 500 ns is predicted for an eighty-bit multiplier.
Resource Type	Masters Thesis
Date Available	2014-04-14T21:33:30+00:00
Date Issued	1966-08-23
Degree Level	Master's
Degree Name	Master of Science (M.S.)
Degree Field	Electrical and Electronics Engineering
Degree Grantor	Oregon State University
Commencement Year	1967
Advisor	Stone, Louis N.
Academic Affiliation	Electrical and Electronics Engineering
Non-Academic Affiliation	Oregon State University. Graduate School
Subject	Analog multipliers Electronic digital computers
Rights Statement	Copyright Not Evaluated
Publisher	Oregon State University
Peer Reviewed	No
Language	English [eng]
Digitization Specifications	File scanned at 300 ppi using Capture Perfect 3.0 on a Canon DR-9050C in PDF format. CVista PdfCompressor 5.0 was used for pdf compression and textual OCR.
Replaces	http://hdl.handle.net/1957/47297

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