Implementation and comparison of two wakeup logic for out-of-order superscalar microprocessors Public Deposited

http://ir.library.oregonstate.edu/concern/graduate_thesis_or_dissertations/c534fr699

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  • The wakeup logic in out-of-order superscalar microprocessors is responsible for resolving the data dependency hazard between instructions. Its performance is critical because it may prevent the processor to have deeper pipelines or to achieve the highest IPC (Instructions Per Cycle) possible. In this thesis, we implemented the circuit and layout for two types of wakeup logic (CAM-type and RAM-type) used in the modem microprocessors. These two implementations are simulated extensively using a circuit level simulator - HSPICE, with full parasitic loads. We, then, made comparison between the CAM-type and RAM-type wakeup circuits. From the simulation results, the CAM-type wakeup logic has a better performance than the RAM-type wakeup logic if a larger number of physical registers is employed by the processor. The performance impacts caused by varying the other superscalar design parameters, such as instruction window size and issue width, are not much different for both types of wakeup logic implementations.
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  • description.provenance : Approved for entry into archive by Patricia Black(patricia.black@oregonstate.edu) on 2012-07-25T17:19:14Z (GMT) No. of bitstreams: 1 LeeHsienYen2003.pdf: 965822 bytes, checksum: 329c738f7a67cbffaf4a17069a6df4ec (MD5)
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