A subranging analog to digital converter using four bit pipepline Public Deposited

http://ir.library.oregonstate.edu/concern/graduate_thesis_or_dissertations/cn69m868z

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  • This thesis presents the design of a 10 bit Analog to Digital Converter which consists of a 6 bit flash followed by a 4 bit pipeline architecture. The total system is described and the 4 bit pipeline is implemented on a bipolar process. The objective of this research is to provide an alternative approach to high speed ADC designs and to implement a pipeline ADC which samples at greater speeds than those achieved with presently existing CMOS pipeline designs. This paper presents the complete architecture, the cell design and simulated performance for each block in the pipeline, and the measured results for the four bit pipeline implementation.
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  • File scanned at 300 ppi (Monochrome, 8-bit Grayscale) using ScandAll PRO 1.8.1 on a Fi-6770A in PDF format. CVista PdfCompressor 4.0 was used for pdf compression and textual OCR.
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  • description.provenance : Approved for entry into archive by Patricia Black(patricia.black@oregonstate.edu) on 2013-01-10T21:58:36Z (GMT) No. of bitstreams: 1 PressStephenE1993.pdf: 4951192 bytes, checksum: cf67ce9a92520ffa7cf3dfee94e8de5a (MD5)
  • Figures in original document are black and white photocopies. Best scan available.
  • description.provenance : Approved for entry into archive by Patricia Black(patricia.black@oregonstate.edu) on 2013-01-10T21:24:13Z (GMT) No. of bitstreams: 1 PressStephenE1993.pdf: 4951192 bytes, checksum: cf67ce9a92520ffa7cf3dfee94e8de5a (MD5)
  • description.provenance : Submitted by Kaylee Patterson (kdpscanner@gmail.com) on 2013-01-10T21:16:17Z No. of bitstreams: 1 PressStephenE1993.pdf: 4951192 bytes, checksum: cf67ce9a92520ffa7cf3dfee94e8de5a (MD5)
  • description.provenance : Made available in DSpace on 2013-01-10T21:58:36Z (GMT). No. of bitstreams: 1 PressStephenE1993.pdf: 4951192 bytes, checksum: cf67ce9a92520ffa7cf3dfee94e8de5a (MD5) Previous issue date: 1993-01-26

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