Design techniques for PVT tolerant phase-locked loops Public Deposited

http://ir.library.oregonstate.edu/concern/graduate_thesis_or_dissertations/dr26z259w

Descriptions

Attribute NameValues
Creator
Abstract or Summary
  • The continued scaling of deep-submicron CMOS technology enables low-voltage high-frequency phase-locked loops (PLLs) to be fully integrated in complex mixed-signal systems. However, fluctuations due to the manufacturing process and variations in environmental conditions, such as supply voltage and temperature, are also significantly increased. As a result, the performance of PLLs that are susceptible to process, voltage, and temperature (PVT) variations are dramatically affected. To truly benefit from process scaling, PVT tolerant designs of high-performance PLLs are essential. In this dissertation, circuit techniques that can mitigate the impacts of PVT variations on PLL performance are presented. In the context of ring voltage-controlled oscillator (VCO) based PLLs, an on-chip calibration technique for reducing the supply voltage sensitivity is described. This method rejects supply noise while avoiding the use of supply regulation, which makes it more desirable in the design of low-voltage high-performance ring VCOs. In a wide-tuning range LC-VCO based PLL frequency synthesizer, design techniques for maintaining a constant loop bandwidth are presented. Having a constant loop bandwidth that is insensitive to PVT variations helps PLL frequency synthesizers to achieve optimum performance in all frequency bands. The proposed circuit techniques are validated by measurement results obtained from prototype chips. The concepts that have been presented in the context of analog PLL implementations can be easily migrated to digital PLLs.
Resource Type
Date Available
Date Copyright
Date Issued
Degree Level
Degree Name
Degree Field
Degree Grantor
Commencement Year
Advisor
Committee Member
Academic Affiliation
Non-Academic Affiliation
Keyword
Subject
Rights Statement
Language
File Format
File Extent
  • 804962 bytes
Replaces
Additional Information
  • description.provenance : Approved for entry into archive by Julie Kurtz(julie.kurtz@oregonstate.edu) on 2007-01-25T18:11:26Z (GMT) No. of bitstreams: 1 ting_thesis.pdf: 804962 bytes, checksum: 34fd194b097aa536ddefeb4ac84b9e8a (MD5)
  • description.provenance : Made available in DSpace on 2007-01-29T18:42:56Z (GMT). No. of bitstreams: 1 ting_thesis.pdf: 804962 bytes, checksum: 34fd194b097aa536ddefeb4ac84b9e8a (MD5)
  • description.provenance : Submitted by Ting Wu (wut@onid.orst.edu) on 2007-01-18T22:18:46Z No. of bitstreams: 1 ting_thesis.pdf: 804962 bytes, checksum: 34fd194b097aa536ddefeb4ac84b9e8a (MD5)

Relationships

Parents:

This work has no parents.

Last modified

Downloadable Content

Download PDF

Items