Investigating new design alternatives for a radix-2 modular multiplier kernal and I/O subsystem Public Deposited

http://ir.library.oregonstate.edu/concern/graduate_thesis_or_dissertations/fx719p75x

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  • A main arithmetic operation for cryptographic systems is modular exponenti- ation. Exponentiation is computed by a long sequence of modular multiplications. Modular multiplication can be implemented in a general-purpose processor or a dedicated hardware, but dedicated hardware tends to be faster than a processor. Modular multiplication is a time-consuming operation, and therefore it requires a fast and ef cient algorithm that can be suitably implemented in hardware. Mont- gomery multiplication algorithm is one of these ef cient algorithms. There are several designs that are implemented based on the Montgomery algorithm. Most of them are xed-precision implementations which means that the system can not perform the multiplication if the operand size is larger than the precision of the system datapath. Its lack of flexibility has led to a new design that can perform the multiplication for operands of any size | a scalable architecture. The hardware implementation of the scalable Montgomery Multiplier (MM) is composed of the kernel and the I/O interface. The main function of the I/O is to interact with both the host system and the kernel. Multiplication operands are loaded from software running on the host system and then stored inside the I/O. These operands are transferred to the kernel when they are needed during the computation. Moreover, the temporary results from the kernel are also stored inside the I/O. All major goals of this thesis work involve the investigation of design alterna- tives for the MM architecture. The rst goal is to investigate an alternate design for the kernel. The second one is to develop a new design for the I/O subsystem. As a nal goal, the generated VHDL code must be ported to a Field Programmable Gate Array (FPGA). That will take advantages of the Xilinx technology, showing the exibility of the scalable MM design in a FPGA chip.
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