The design of a reduced instruction set computer using a silicon compiler Public Deposited

http://ir.library.oregonstate.edu/concern/graduate_thesis_or_dissertations/g158bk81m

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  • The objective of this thesis is to describe the design and implementation of a VSLI reduced instruction set computer (RISC). The RISC machine constitutes a new style of computer architecture. It differs significantly from the complex instruction set computer architectures (CISC) of the past. RISC architectures are characterized by their high performance, simple instruction sets, minimal hardware requirements, and their ability to support block structured programming languages adequately. In this thesis a 16-bit single chip RISC was designed using the Genesil Silicon Compiler. It has 14 instructions, an overlapped register window structure, and on chip memory. It can execute most instructions in a single clock cycle, including procedure calls and returns. The peak performance of this chip is approximately 6 MIPS. The chip was implemented in 2 micron CMOS technology. The chip size is 516.54 X 514.27 mils. This chip has not been fabricated.
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  • description.provenance : Approved for entry into archive by Patricia Black(patricia.black@oregonstate.edu) on 2013-05-29T15:42:29Z (GMT) No. of bitstreams: 1 ZhangLicheng1990.pdf: 565717 bytes, checksum: abb7a61c44927baaa08dd8883d0dd2f0 (MD5)
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  • description.provenance : Approved for entry into archive by Patricia Black(patricia.black@oregonstate.edu) on 2013-07-30T20:48:03Z (GMT) No. of bitstreams: 1 ZhangLicheng1990.pdf: 565717 bytes, checksum: abb7a61c44927baaa08dd8883d0dd2f0 (MD5)
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