Silencer! : a tool for substrate noise coupling analysis Public Deposited

http://ir.library.oregonstate.edu/concern/graduate_thesis_or_dissertations/g158bm41v

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  • This thesis presents Silencer!, a fully automated, schematic-driven tool for substrate noise coupling simulation and analysis. It has been integrated in the CADENCE DFII environment and seamlessly enables substrate coupling analysis in a standard mixed-signal design flow. Silencer! aids IC designers in the analysis of substrate noise coupling at different levels of hierarchy - from a level where only an approximate layout of the transistors is known to a level that incorporates various parasitic elements. It can be used for layout optimization to reduce substrate cross-talk noise between circuitry that injects noise into the substrate and other circuitry that is sensitive to it. Examples in a TSMC 0.35μm heavily doped process have been simulated and the results are in good agreement with measured fabricated chips.
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  • description.provenance : Approved for entry into archive by Linda Kathman(linda.kathman@oregonstate.edu) on 2009-05-27T21:30:29Z (GMT) No. of bitstreams: 1 Patrick_Birrer.pdf: 1588391 bytes, checksum: 6075579c17b8067f576bdba8dfdc4e59 (MD5)

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