Tolerating processor-memory performance gap Public Deposited

http://ir.library.oregonstate.edu/concern/graduate_thesis_or_dissertations/gt54kq552

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  • While the performance gap between microprocessors and main memory is ever increasing each year, cache memory has been a bridge to alleviate this discrepancy. In this thesis proposal, we introduce three techniques to tolerate this processor and memory speed imbalance. First, we propose the bloom filter scheme to identify which load operant could cause cache miss. Second, we explore a new fault-tolerant microarchitecture to detect transient error occurs. Third, we proposed a novel hardware-only mechanism to solve pointer-chasing problem in Link-list Data Structure application. The simulation shows that the bloom filter may filter out 99% of cache miss. The new fault-tolerant microarchitecture reduce the penalty caused by detecting instruction error about 1.8-13%. The hardware-only data prefetch mechanism accurate predict over 80% of irregular address pattern and improve the performance by 7%.
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  • description.provenance : Approved for entry into archive by Patricia Black(patricia.black@oregonstate.edu) on 2012-07-02T17:44:23Z (GMT) No. of bitstreams: 1 LaiShih-Chang2002.pdf: 4792372 bytes, checksum: 2a2a43fd1841440b4e61d472526533b4 (MD5)
  • description.provenance : Approved for entry into archive by Patricia Black(patricia.black@oregonstate.edu) on 2012-07-02T17:01:32Z (GMT) No. of bitstreams: 1 LaiShih-Chang2002.pdf: 4792372 bytes, checksum: 2a2a43fd1841440b4e61d472526533b4 (MD5)
  • description.provenance : Submitted by Eric Hepler (ehscanner@gmail.com) on 2012-06-25T17:29:13Z No. of bitstreams: 1 LaiShih-Chang2002.pdf: 4792372 bytes, checksum: 2a2a43fd1841440b4e61d472526533b4 (MD5)
  • description.provenance : Made available in DSpace on 2012-07-02T17:44:23Z (GMT). No. of bitstreams: 1 LaiShih-Chang2002.pdf: 4792372 bytes, checksum: 2a2a43fd1841440b4e61d472526533b4 (MD5) Previous issue date: 2002-10-31

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