An integrated MOS addressing circuit Public Deposited

http://ir.library.oregonstate.edu/concern/graduate_thesis_or_dissertations/h128nh85k

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  • This paper is a study of the design of an integrated MOS addressing circuit by using the modified two-phase dynamic shift register. This modified circuit is compared to the conventional two-phase dynamic SR and discussed briefly. The resulting circuit shows several advantages to improve the essential conditions of integrated circuit design and fabrication. Four stages of this dynamic SR are designed on a single monolithic chip. Each stage consists of seven devices and two intentionally added capacitors. A suggestion to imply that more stages can be used in any sequential digital system is given. It is shown that the operation is at AC and the operating frequency is ranged between 200 KHz and 1 MHz clock rates.
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  • description.provenance : Made available in DSpace on 2014-02-25T19:18:12Z (GMT). No. of bitstreams: 1 ChangKiS1970.pdf: 650354 bytes, checksum: 810cefa6bc1e97ec59f5ef8c935ccdf1 (MD5) Previous issue date: 1969-06-12
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  • description.provenance : Approved for entry into archive by Katy Davis(kdscannerosu@gmail.com) on 2014-02-25T19:18:12Z (GMT) No. of bitstreams: 1 ChangKiS1970.pdf: 650354 bytes, checksum: 810cefa6bc1e97ec59f5ef8c935ccdf1 (MD5)
  • description.provenance : Approved for entry into archive by Patricia Black(patricia.black@oregonstate.edu) on 2014-02-25T14:38:02Z (GMT) No. of bitstreams: 1 ChangKiS1970.pdf: 650354 bytes, checksum: 810cefa6bc1e97ec59f5ef8c935ccdf1 (MD5)

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