Graduate Thesis Or Dissertation
 

Micropower incremental analog-to-digital converters

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https://ir.library.oregonstate.edu/concern/graduate_thesis_or_dissertations/hh63sz808

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  • Incremental ADCs (IADCs) have many advantages for low-frequency high-accuracy data conversion—they are easy to multiplex between channels, need simpler digital decimation filter, and allow extended counting with a Nyquist-rate ADC. A single-loop incremental ADC was designed and fabricated in 90 nm for a biosensor interface circuit. It incorporates one integrator, and uses noise-coupling technique to achieve second-order noise-shaping. The use of feed-forward coupling and multi-bit internal quantizer allows low swing at the integrator, and hence low-power operation. The measured SNR is 74 dB within a signal bandwidth 2 kHz, and a 14 μW power consumption. A new two-step IADC was proposed for 250 Hz bandwidth sensor interface circuits. It extends the order of a conventional incremental ADC from N to (2N-1) by way of a two-step operation. However, it only needs the same circuitry as the Nth-order IADC. A second-order loop filter was designed and fabricated by 2.5V I/O devices in 65 nm to demonstrate this concept to achieve third-order noise-shaping performance. Operated at sampling frequency 96 kHz, the measured dynamic range is 99.8 dB relative to a maximum input 2.2 VPP. The measured maximum SNDR was 91 dB with a 2.2 V[subscript PP] input amplitude. The ADC core area is 0.2 mm², and the IADC consumed only 11.7 μW. A new incremental ADC with multi-step extended-counting was proposed for sensor interface conversion. A 1st-order feedforward modulator was used for the coarse conversion, and the residue voltage was quantized by re-using the modulator for the fine conversion. Then, the circuit was re-configured as a counting ADC to quantize the residue voltage. The three steps of the circuits perform 15-bit quantization by 5-bit/step. A first-order IADC could only achieve 6.6-bit performance within the same conversion time of 96 clock periods. Reusing the first-order circuits, extra 8.4-bit is thus achieved.
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