Comparison and analysis of current-mode logic circuits with differential and static CMOS Public Deposited

http://ir.library.oregonstate.edu/concern/graduate_thesis_or_dissertations/j098zd09c

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  • This thesis describes the analysis and comparison of Folded Source-Coupled Logic (FSCL) with standard static CMOS, cascode voltage-switch logic and differential split-level logic gates. The advantages of FSCL are low switching noise and high operating speed. The effect of voltage and device scaling on these topologies is evaluated in terms of average delay, power dissipation at maximum frequency, power-delay-product and current spike noise. Several two-summand adders are designed and simulated using MOSIS 1-μm CMOS process parameters and evaluations are performed in terms of area, delay, noise and power dissipation.
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  • File scanned at 300 ppi (Monochrome, 8-bit Grayscale) using ScandAll PRO 1.8.1 on a Fi-6670 in PDF format. CVista PdfCompressor 4.0 was used for pdf compression and textual OCR.
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  • description.provenance : Approved for entry into archive by Patricia Black(patricia.black@oregonstate.edu) on 2013-01-08T22:49:17Z (GMT) No. of bitstreams: 1 ShrivastavaManuB1994.pdf: 1684255 bytes, checksum: a189882537a1420caf179c2c50c793d0 (MD5)
  • description.provenance : Made available in DSpace on 2013-02-12T17:15:48Z (GMT). No. of bitstreams: 1 ShrivastavaManuB1994.pdf: 1684255 bytes, checksum: a189882537a1420caf179c2c50c793d0 (MD5) Previous issue date: 1994-02-07
  • description.provenance : Approved for entry into archive by Patricia Black(patricia.black@oregonstate.edu) on 2013-02-12T17:15:48Z (GMT) No. of bitstreams: 1 ShrivastavaManuB1994.pdf: 1684255 bytes, checksum: a189882537a1420caf179c2c50c793d0 (MD5)
  • description.provenance : Submitted by John Valentino (valentjo@onid.orst.edu) on 2012-12-18T22:27:48Z No. of bitstreams: 1 ShrivastavaManuB1994.pdf: 1684255 bytes, checksum: a189882537a1420caf179c2c50c793d0 (MD5)

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