Comparison and analysis of jitter in CMOS ring oscillators Public Deposited

http://ir.library.oregonstate.edu/concern/graduate_thesis_or_dissertations/j9602369p

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  • A comparison and analysis of jitter for five different architectures of ring oscillators using a novel simulation technique developed by Professor Forbes' group is presented. Ring oscillators have become an essential building block in many digital and synchronous communications system due to their integrated nature and are widely used in phase-locked loops (PLL) for clock and data recovery, frequency synthesis and on-chip clock distribution and generation. The five different architecture circuits were injected with white noise and flicker noise according to our simulation technique and their jitter performance has been analyzed.
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