Modeling and development of p-type thin-film transistors Public Deposited

http://ir.library.oregonstate.edu/concern/graduate_thesis_or_dissertations/jw827d977

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  • The primary focus of this thesis involves modeling and development of p-type thin-film transistors (p-TFTs), moving towards the realization of a filly transparent thin-film transistor (TTFT). The modeling portion of this thesis emphasizes the development of physics-based TFT models, specifically focusing on the elucidation of non-ideal current-voltage characteristic behavior. A 3-layer model is introduced, which includes three current paths from source to drain via an insulator/semiconductor accumulation layer, a bulk conduction path, and a surface conduction path. In addition, series resistance is incorporated into the 3-layer model to account for non-ideal source/drain metal-semiconductor contacts, yielding a non-analytical model which is solved iteratively. In addition to TFT model development, field-effect, effective, average, and incremental mobility trends are simulated. The development portion of this thesis is devoted to the design, fabrication, and testing of p-type TFTs with BaCuSF channel layers. All of the p-type TFTs fabricated to date exhibit non-idealities in the form of high output conductance and the inability for the drain-to-source current to be shut off. It is concluded that the cause of these problems is a high hole carrier concentration in the BaCuSF channel that results in a large amount of drain-to-source current being shunted through the bulk of the semiconductor. A new device structure is proposed to alleviate this problem and to ensure that the source/drain contacts to the semiconductor channel are Ohmic in nature.
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