Design and analysis techniques for nano-joule ADCs and sampling linearity Public Deposited

http://ir.library.oregonstate.edu/concern/graduate_thesis_or_dissertations/jw827f477

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  • Two aspects of ADC system performance are addressed in this work. First, the combination of the ADC and its associated reference are co-designed for an energy constrained remote sensing system. Second, sampling linearity is mathematically analyzed as a function of frequency to provide enhanced understanding into an ADC's requisite sampling network. Low energy analog design techniques for emerging systems powered by energy scavenging are demonstrated in the context of an analog-to-digital converter system. It is composed of a variable gain sample-and-hold amplifier, a low voltage reference, a 1.5 bit per stage 9-b cyclic ADC, clock generation, reference buffers, and control logic. A novel Class-AB current mirror amplifier together with correlated level shifting enable wide swing and enhanced gain operation at low supply voltages while reducing current draw. The use of subthreshold MOSFETs instead of bipolar junction transistors allows the use of traditional bandgap circuit techniques to be employed for a 530 mV reference that is less than a diode voltage drop. Operating from a 750 mV supply voltage and 20.48 kSPS, the ADC and reference consume 9.5μA and 1.5μA, respectively. The measured 7.9-bit ENOB results in an FoM of 2.24 pJ/step. The total energy consumption is 535 pJ per conversion for the entire system. A novel model predicts tracking nonlinearity (NL) in the form of harmonic distortion (HD) for weakly NL (i.e. SFDR>30dBc) first order open-loop sampling circuits. The mechanisms for the NL are exponential settling, amplitude modulation, phase modulation and discrete-time modulation. The model demonstrates that HD typically increases at 20 dB per decade over most standard operating ranges and is a function of input frequency, sampling bandwidth, input amplitude, the sample rate and component nonlinearity. Application of the model is reduced to the equivalent of frequency-independent nonlinearity analysis over this range, requiring only a Taylor series expansion of the NL time constant. Design insight is given for common MOS switch types, revealing a high correlation between HD and bandwidth. The first method to quantify the trade-off between thermal noise (SNR) and linearity (SFDR) for sampling circuits is presented. Measured HD2, HD3, HD4, and HD5 versus frequency at multiple sample rates of a Sample and Hold test chip fabricated in a 0.25μm 1P5M CMOS process and Spectre simulation results support the findings. The results broadly apply to switched capacitor circuits in general and sampling circuits specifically, regardless of technology.
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