Graduate Thesis Or Dissertation
 

Low-power high-linearity digital-to-analog converters

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https://ir.library.oregonstate.edu/concern/graduate_thesis_or_dissertations/m900nx12w

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  • In this thesis work, a design of 14-bit, 20MS/s segmented digital-to-analog converter (DAC) is presented. The segmented DAC uses switched-capacitor configuration to implement 8 (LSB) + 6 (MSB) segmented architecture to achieve high performance for minimum area. The implemented LSB DAC is based on quasi-passive pipelined DAC that has been proven to provide low power and high speed operation. Typically, capacitor matching is the best among all integrated circuit components but the mismatch among nominally equal value capacitors will introduce nonlinear distortion. By using dynamic element matching (DEM) technique in the MSB DAC, the nonlinearity caused by capacitor mismatch is greatly reduced. The output buffer employed direct charge transfer (DCT) technique that can minimize kT/C noise without increasing the power dissipation. This segmented DAC is designed and simulated in 0.18 μm CMOS technology, and the simulated core DAC block only consumes 403 μW.
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Déclaration de droits
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La vignette Titre Date de téléchargement Visibilité actes
file details KuoMingHung2012.pdf 2017-08-08 Public Télécharger