VLSI implementation of adaptive BIT/serial IIR filters Public Deposited

http://ir.library.oregonstate.edu/concern/graduate_thesis_or_dissertations/m900nx21v

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  • A new structure for the implementation of bit/serial adaptive IIR filter is presented. The bit level system consists of gated full adders for the arithmetic unit and data latches for the data path. This approach allows recursive operation of the IIR filter to be implemented without any global interconnections, minimal delay time, chip area and I/O pins. The coefficients of the filter can be updated serially in real time for time invariant and adaptive filtering. A fourth order bit/serial IIR filter is implemented on a 2 micron CMOS technology clocked at 55 MHz.
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  • File scanned at 300 ppi (Monochrome) using ScandAll PRO 1.8.1 on a Fi-6770A in PDF format. CVista PdfCompressor 5.0 was used for pdf compression and textual OCR.
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  • description.provenance : Approved for entry into archive by Patricia Black(patricia.black@oregonstate.edu) on 2013-01-31T20:14:52Z (GMT) No. of bitstreams: 1 BadyalRajeev1992.pdf: 856920 bytes, checksum: 67f7e35de3c12413aae85c00a1fb5763 (MD5)
  • description.provenance : Submitted by Kaylee Patterson (kdpscanner@gmail.com) on 2013-01-31T19:42:58Z No. of bitstreams: 1 BadyalRajeev1992.pdf: 856920 bytes, checksum: 67f7e35de3c12413aae85c00a1fb5763 (MD5)
  • description.provenance : Made available in DSpace on 2013-01-31T20:19:16Z (GMT). No. of bitstreams: 1 BadyalRajeev1992.pdf: 856920 bytes, checksum: 67f7e35de3c12413aae85c00a1fb5763 (MD5) Previous issue date: 1992-01-29
  • description.provenance : Approved for entry into archive by Patricia Black(patricia.black@oregonstate.edu) on 2013-01-31T20:19:16Z (GMT) No. of bitstreams: 1 BadyalRajeev1992.pdf: 856920 bytes, checksum: 67f7e35de3c12413aae85c00a1fb5763 (MD5)

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