High-performance low-power microprocessor circuits Public Deposited

http://ir.library.oregonstate.edu/concern/graduate_thesis_or_dissertations/mc87pt54w

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  • This thesis will discuss two critical components of a digital system -- domino logic styles and flip-flops. In today's microprocessors, both domino logic and flip-flops are essential to high-performance and low-power design. Two new domino logic styles are presented and analyzed, Double Edge Triggered (DET) and Double Data Rate (DDR) Domino. Using a CMOS 0.25μm MOSIS model, HSPICE simulations show that a DET & DDR 8-bit adder has a maximum throughput of l.6Gops (Giga Operations per second) and 2Gops, respectively, while a conventional domino adder has only 1Gops. In addition, this thesis proposes a novel master-slave flip-flop. This flip-flop is compared with other known flip-flop structures. Using a CMOS 0.35μm MOSIS model, the new flip-flop was simulated to have an optimal power-delay product. The proposed flip-flop consumes very low power, while having a very small clock load and data load.
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  • description.provenance : Made available in DSpace on 2012-08-24T18:54:04Z (GMT). No. of bitstreams: 1 HsuStevenK2001.pdf: 1544934 bytes, checksum: e6290fa808321665a1f751aecb2311fd (MD5) Previous issue date: 2001-02-02
  • description.provenance : Approved for entry into archive by Patricia Black(patricia.black@oregonstate.edu) on 2012-08-24T18:54:04Z (GMT) No. of bitstreams: 1 HsuStevenK2001.pdf: 1544934 bytes, checksum: e6290fa808321665a1f751aecb2311fd (MD5)
  • description.provenance : Approved for entry into archive by Patricia Black(patricia.black@oregonstate.edu) on 2012-08-24T18:51:39Z (GMT) No. of bitstreams: 1 HsuStevenK2001.pdf: 1544934 bytes, checksum: e6290fa808321665a1f751aecb2311fd (MD5)
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