Analysis and measurement of charge injection in switched-capacitor circuits Public Deposited

http://ir.library.oregonstate.edu/concern/graduate_thesis_or_dissertations/ms35td013

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  • It has been verified by theoretical analysis, circuit simulation and test that two switch transistors in parallel in a simple sample and hold circuit can be achieve high speed with low error voltage due to charge injection. The wide transistor provides low RC time constant when it is closed and the narrow one ensures a low error voltage. However, tradeoff can be made in a specific application. A concise analytical expression for switch-induced error voltage on a switched capacitor is derived in this thesis. It can help designer to make the optimum decision. Experimentally, it was found that the optimum size of the wide transistor is several times wider than the narrow one. Delayed clock scheme can be used to make charge injection signal-independent in a basic integrator structure. Using two transistors with different sizes and clock duty cycles in parallel can take advantage of the fast speed of the wide transistor and the small charge injection error of the small transistor. However, the combination of the two devices, including the size and clock duty cycles, should be chosen carefully to achieve the improvement.
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  • description.provenance : Made available in DSpace on 2012-09-27T17:57:15Z (GMT). No. of bitstreams: 1 ShenMin1998.pdf: 2306476 bytes, checksum: 7a69d62b3c6de09205d15a74a4b40d24 (MD5) Previous issue date: 1998-03-10
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