Multiple-fault detection in iterative arrays Public Deposited

http://ir.library.oregonstate.edu/concern/graduate_thesis_or_dissertations/n583xz41x

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  • With the advent of LSI, iterative forms of realization of digital systems are becoming increasingly popular with system designers. Many problems occurring in digital computer design render themselves suitable for iterative realization. These include adders, arithmetic logic units, coding and decoding circuits and so on. Fault-free functioning of such systems is very important, and this dissertation develops multiple-fault detection tests for the above class of arrays: namely, one and two dimensional iterative arrays. The difference from previous work is that each cell is modeled in terms of its state graph behavior as opposed to more conventional techniques, which emphasize the sensitization of paths representing the electronics of the realization. Using the transition matrix representation of the flow table of an arbitrary cell in the array, the fault detection test is generated by an algorithm that involves the comparison of the rows in the matrix corresponding to the normal and faulty state-behavior of the cell. The tests generated are such that they test simultaneously more than one cell in the array for the given fault. A graph-theoretic condition is imposed on the state graph of the cell, for the existence of such tests. The case of two-dimensional array is viewed as equivalent to a one-dimensional array by compression, either horizontally or vertically. This enables the extension of the fault-detection test algorithm for the one-dimensional array to the two-dimensional array without further modification.
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