|Abstract or Summary
- Data converters are ubiquitous building blocks of a signal chain. The rapid increase in
communication and connectivity devices presents new avenues for pushing the state of
the art analog to digital converters. Techniques for improving resolution, bandwidth,
linearity and bit-error rate, while reducing the power, energy and area is the motivation
for this research. This research focuses on achieving this goal by enabling circuit
techniques, architecture techniques and calibration methods. The following techniques
are proposed for enabling power, area and energy efficient analog to digital converter
1. A capacitor switching scheme for successive approximation ADC is introduced to
enable 93.4% energy reduction and 75 % reduction in capacitor area as compared to a
conventional SAR ADCs.
2. Asynchronous correlated level shifting technique for improving current source linearity
and power supply rejection ratio of zero crossing based circuits is proposed. This
technique enables asynchronous ADC architectures for energy efficient system.
3. Unified gain enhancement model is proposed to catalogue gain enhancement techniques.
Class-A+ and Replicated Parallel Gain Enhancement (RPGe) amplifiers are
introduced as parallel gain enhancement techniques for switched capacitor circuits. A
prototype pipelined ADC using RPGE amplifier achieves 74.9 dB SNDR, 90.8 dB SFDR,
87 dB THD at 20 MS/s. Built in 1P4M 0.18 μm technology and operating at 1.3 V supply,
the ADC consumes 5.9 mW. The ADC occupies 3.06 sq. mm and has a figure of
merit of 65 fJ /conversion step. Extracted simulation results of the prototype pipeline
ADC using dynamic RPGE amplifier achieve 74 dB SNDR, 90 dB SFDR, and 85 dB
THD at 30 MS /s in a 0.18 μm process. The ADC consumes 6.6 mW from a 1.3 V
supply and achieves a figure of merit of 40 fJ/C-S.
4. A low-gain amplifier based V-T converter is utilized along with a TDC to replace
the function of flash ADC and the DAC references in a pipeline ADC. The simulated/
extracted performance of the chip is 12bit, 100 MHz in 65nm process while consuming
approximately 8-9 mA from 1 V supply.
5. A measurement technique for detecting and correcting bit-error rate in ADCs is proposed.
This multi-path ADC technique squares the bit-error rate of the ADC without
consuming additional analog power. The area increase is negligible compared to the
conventional modular redundancy techniques. This technique can be applied to digitally
detect and correct single event transients for ADCs. A three-path ADC can restore the
ADC performance independent of the input frequency and number of errors in a single
6. LMS algorithm is used to estimate the VCO non-linearity by using the VCO as a
Nyquist ADC and utilizing a slow but accurate ADC. The simulated ADC performance
improves from 5 bits to 7.8 bits by using a second order fit to the VCO non-linearity.