Graduate Thesis Or Dissertation
 

Priority structures for multiaccess memory systems

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https://ir.library.oregonstate.edu/concern/graduate_thesis_or_dissertations/nz806211c

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  • The quest for greater computer-system speed has brought about a continuing increase in the parallelism of these systems. In particular, the number of processors and other devices which are required to access the same core-memory not for economy, but for the advantages to be derived from using the memory as an exchange for data and control information has increased markedly. That portion of such multiaccess systems which allocates the memory accesses available at a given instant of time among the devices then requesting access to memory is denominated the priority structure. These attributes are desirable in a priority structure: 1. It should service all requesting devices within the limits of their patience; i. e. the latency of each memory-accessing channel should be less than the patience of the corresponding device. 2. It should be efficient in that all accesses available from the core-memory are made available to devices. 3. It should be modularly constructed and reconfigurable so that no single component is absolutely necessary for system operation; i. e. it should introduce no intrinsic point of permanent articulation. Priority structures used heretofore, principally strict-priority and first come-first serve, do not exhibit all of these characteristics: First come-first serve systems, although efficient, are incompatible with devices of small patience unless intrinsic points of permanent articulation are allowed. Strict-priority systems, are generally not 100% efficient, have variable channel latencies, but are favorable to the elimination of articulation points. Their inadequacies are not a result of the idiosyncrasis of a particular hardware implementation but are shown to be, in each case, a fundamental shortcoming of the service discipline itself, when applied to multiaccess memory systems. An alternate discipline, limited-latency, is developed which does exhibit all of the desired characteristics. In an example of this discipline, each multiplexor, at each level, in the memory-access structure is required to contain a cycle-counter, the states of which are decoded so as to guarantee each input channel some fraction of the total number of cycles available to that multiplexor. Necessary, or desirable, restrictions on the sequence of guaranteed-fractions to be so obtained are derived and their consequences are discussed. Finally, it is shown that the limited-latency structure is a general schema, independent of ad hoc hardware considerations, which can serve as the basis for particular designs. (It does, in fact, include first come-first serve and strict-priority as special cases.)
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