Enabling metal-fill-aware design of integrated circuits Public Deposited

http://ir.library.oregonstate.edu/concern/graduate_thesis_or_dissertations/pk02cg016

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  • In advanced integrated circuit (IC) processes, the metal fill inserted to meet foundry imposed density requirements degrades the performance of interconnects and passive components which ultimately affects the overall circuit performance. Accounting for this degradation through electromagnetic and equivalent circuit modeling is becoming a critical aspect of IC design. However, electromagnetic simulation of interconnects and passive components including metal fill quickly becomes prohibitive due to the large problem complexity while the modeling methods in the literature are limited in accuracy and ignore important effects. This thesis investigates fast and scalable modeling methods for interconnects and spiral inductors in the presence of metal fill. We demonstrate a novel three dimensional problem reduction approach to model the parasitic capacitance due to metal fill in multiconductor interconnects. Further, we demonstrate a unique technique for modeling metal fill in spiral inductors. We present a systematic on-wafer measurement characterization approach for model verification. Ultimately, the research presented in this thesis will enable efficient metal-fill-aware design of integrated circuits through fast and accurate models for interconnects and passive components in the presence of metal fill.
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