Graduate Thesis Or Dissertation

 

Reduced instruction set computer memory architectures Public Deposited

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https://ir.library.oregonstate.edu/concern/graduate_thesis_or_dissertations/pn89db537

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  • This thesis describes the design of a Reduced Instruction Set Computer. Its instruction memory utilizes a unique cache architecture and a two-stage memory pipelining technique. Because of the bandwidth of the 64-bit instruction bus, instruction prefetching is possible and is implemented. The data memory is bridged by a four-way set-associative cache which uses a mix of write-through and copy-back memory write-back policies. A four-stage execution pipeline is used to accelerate instruction execution. Scoreboard bits are implemented for the general register set. The use of the scoreboard reduces data dependency problems. The cache architecture is specifically designed to handle programs including branch instructions. Simulation results show that the CPU executes cold-start simulated programs in nearly half the time of that of other RISC microprocessors.
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