The release of the IEEE802.15.6 standard has led to increased interest in low-power technologies for wireless body-area-networks (WBANs). The power dissipation, supply voltage, and die area are some of the most important criteria for successful WBAN implementations. Digital-intensive RX architectures can potentially result in sub-1V operation with significant reductions in power consumption and area, but require system and circuit-level innovations to achieve desired sensitivity and linearity. A PSK receiver (RX) is proposed that employs a digital-intensive architecture based on sub-sampling, Q-enhancement, and digital IF to enable lowpower (1.3mW) and low-voltage (0.6V) operation. Implemented in 65nm CMOS, this work is compatible with the IEEE 802.15.6 narrowband physical layer specification and achieves -91dBm and -96dBm sensitivity at 10⁻³ BER for π/4DQPSK and π/2-DBPSK modulation, respectively. The proposed highly-digital architecture and supply voltage scaling lead to a 3x improvement in RX energy efficiency and minimize silicon area consumption (~0.35mm² in 65nm CMOS) while achieving state-of-the-art sensitivity. While this implementation focuses on IEEE 802.15.6 narrowband demodulation, the proposed architecture and circuit techniques are generally applicable to RX targeting ultra-low power consumption for sensor networks.