Graduate Thesis Or Dissertation
 

Minimizing input logic for a sequential network

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https://ir.library.oregonstate.edu/concern/graduate_thesis_or_dissertations/qj72pb86x

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  • A complete procedure of minimizing input logic in designing both completely and incompletely specified synchronous, finite state sequential networks is presented in detail. This procedure consists of three important steps: 1) state simplification, 2) state assignment and 3) input logic realization. Two new ideas are presented in the procedure of minimizing internal states. First, the number in the minimal final class which is chosen from the final class is used as the lower bound of a minimal closed set. Second, the minimal closed set is found by means of the implication graph. The implication graph is also used to find a partition with a substitution property for given internal states in state assignment. This partition always leads to an economical state assignment. Useful and important principles are developed for deriving the input logic set for any type of flipflop. The results provided a much simpler and faster way to derive the input logic than do analytic methods.
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  • File scanned at 300 ppi using Capture Perfect 3.0 on a Canon DR-9050C in PDF format. CVista PdfCompressor 5.0 was used for pdf compression and textual OCR.
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