Graduate Thesis Or Dissertation

Linearity enhancement techniques for data converters

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  • Data converters are essential interface circuits between the analog world that people live in and the digital processors that people live with. Linearity, which often is a tradeoff against other performance criteria, is one of the major performance demands from applications for both analog-to-digital converts (ADC) and digital-to-analog converters (DAC). This dissertation describes several novel linearity enhancement techniques utilizing mainly digital circuits, targeting different data converter architectures allowing their linearity performances to be enhanced without many sacrifices from other features such as conversion bandwidth or power consumption. A background calibration method for flash ADCs was developed. It cancels the error introduced by comparator offsets and component mismatches in reference circuit. The calibration works primarily in the digital domain with small analog hardware overhead. The offsets in the flash ADC are pseudo-randomly and gradually calibrated, thus the accuracy of the ADC is eventually restored. A foreground calibration method for delta-sigma ADCs is also proposed. The fully digital calibration technique extracts the multi-bit feedback DAC error and cancels it in the digital domain. The calibration scheme requires no precision external components and inserts only a small digital block at the modulator feedback path. A new approach of radix-based digital technique for compensating capacitor mismatch of the two-capacitor DAC is introduced. Digital input words are pre-distorted with an ADC-like algorithm before they are fed into the DAC. The proposed methods provide better linearity performance when the DAC is converting higher number of bits. Extra peripheral circuits to achieve the digital compensation are briefly discussed.
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