|Abstract or Summary
- Nowadays, needs for wideband and high accuracy analog-to-digital converter are increasing rapidly in manifold applications such as wireless communication, digital video and other consumer electronics. Besides, low power consumption is required to have longer battery life in portable systems. CMOS technology scaling and innovative modulator topology make the implementation much easier and practicable.
In this dissertation, first, various incremental ADCs are discussed and analyzed. Incremental ADC with extended counting and 2+2 MASH incremental ADC were designed and fabricated in 0.18 2P4M CMOS process to achieve wide bandwidth, high accuracy, and low latency. Incremental ADC with extended counting ADC achieves 91.6dB dynamic range and 77.8dB peak SNDR with 1.25MHz signal band. The total power consumption is 53.5mW. 2+2 MASH incremental ADC achieves 94.2dB dynamic range and 74.8dB peak SNDR up to 1.25MHz signal band. The total power consumption is 67mW.
Secondly, feedback timing relaxed ΔΣ ADC with noise coupling was proposed. Because of the relaxed the feedback timing, we are able to use the low speed comparator and DEM circuitry resulting in low power consumption. Two slightly different prototypes were implemented in 0.18 2P4M CMOS process. Sampling capacitor is separated from DAC capacitor in prototype A while they are shared in prototype B. Even if prototype B has half of noise than prototype A due to the less capacitor at the input branch of the modulator, prototype B suffers from signal dependent reference error. Measurement results of prototype A achieves 90.5dB dynamic range, 81.2dB peak SNDR with 2.1MHz signal band. On the other hand, prototype B achieves 95.6dB dynamic range, 74.2dB peak SNDR up to 2.1MHz signal band under same test environment. Both of two prototypes consume 98mW. Based on the measurement results, prototype B where sampling capacitor is shared with DAC capacitor suffers from higher harmonic distortion than prototype A.
Finally, double noise coupled ΔΣ modulator was proposed. The proposed architecture is less sensitive to finite opamp DC gain effects and complex on clock generator design than the second order noise shaping ΔΣ modulator.