Low power, high performance pseudo-static D flip-flop Public Deposited

http://ir.library.oregonstate.edu/concern/graduate_thesis_or_dissertations/rb68xf94s

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  • Digital systems, in particular microprocessor, have recently experienced phenomena growth in performance. Both technology advancement and clever design have sustained this performance growth. As clock frequency heads into the Ghz range, new circuit design, for both logic and storage, are needed. Such new circuit technology must provide needed performance with minimum power consumption. Flip-flops are essential elements of a digital system. They are used to hold both state information and results. As processor architecture such as superscalar becomes more advanced, the control logic grows more complex resulting in an increasing number of D flip-flops. These flip-flops are all driven by the global clock, which leads to higher power dissipation with increasing clock frequency. One way to reduce power consumption is to send the microprocessor into a sleep mode. Once in this mode, the clock is turned off (at logic low level), forcing the control logic to remain in a standby state. In this thesis, two D flip-flop designs are introduced and compared with conventional designs: dynamic NRC (no race condition) and pseudo-static cascode pull-down. Such design criteria comparisons include speed, power consumption, scaling, noise margin, and metastability.
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