Graduate Thesis Or Dissertation

 

Architecture design of multiplexed incremental analog-to-digital converters Public Deposited

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https://ir.library.oregonstate.edu/concern/graduate_thesis_or_dissertations/rr1722933

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  • Analog-to-Digital Data Converters (ADCs) used in instrumentation and measurements often require high absolute accuracy, including excellent linearity and negligible dc offset. Incremental data converters (IDCs) provide a solution for such measurement applications. Since IDCs are essentially delta-sigma converters with reset operation before each conversion, they retain most of the advantages of conventional [delta sigma] converters, and yet they are capable of offset-free and accurate conversion.Most of the previous research on incremental converters is for single-channel and dc signal applications, where they can perform extremely accurate data conversion with more than 20-bit resolution. In this thesis, the operation and the performance ofIDCs in both frequency and time domain is analyzed. Design techniques for implementing multiplexed IDCs to convert narrow bandwidth ac signals are discussed too. It incorporates the operation principles, modulator topologies, digital filter design and signal-to-noise ratio optimization methodology. The theoretical analysis is verified by simulation results.
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  • description.provenance : Approved for entry into archive by Julie Kurtz(julie.kurtz@oregonstate.edu) on 2008-01-10T18:25:07Z (GMT) No. of bitstreams: 1 MSWord_thesis_1.6.pdf: 383195 bytes, checksum: 7f811994138b33a61ddc68aea341c416 (MD5)
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  • description.provenance : Approved for entry into archive by Linda Kathman(linda.kathman@oregonstate.edu) on 2008-01-16 (GMT) No. of bitstreams: 1 MSWord_thesis_1.6.pdf: 383195 bytes, checksum: 7f811994138b33a61ddc68aea341c416 (MD5)
  • description.provenance : Made available in DSpace on 2008-01-16 (GMT). No. of bitstreams: 1 MSWord_thesis_1.6.pdf: 383195 bytes, checksum: 7f811994138b33a61ddc68aea341c416 (MD5)

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