Substrate noise coupling analysis in 0.18um silicon germanium (SiGe) and silicon on insulator (SOI) processes Public Deposited

http://ir.library.oregonstate.edu/concern/graduate_thesis_or_dissertations/sj139490z

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  • Analysis of substrate noise coupling has been performed for a 0.18¹m lightly doped silicon germanium BiCMOS process. Techniques to minimize noise coupling in the chip and board design are presented, as well as methods for accu- rate modeling for substrate noise coupling simulations. Measurements from a test chip were taken to verify that the modeling approach used in simulation and the substrate noise model obtained using Silencer! is accurate to within 10%. The e®ects of a deep trench moat structure, bulk separation, and die perimeter ring were also tested as possible noise reduction methods. Strategies for simulation and measurement of substrate noise coupling in a 0.18¹m SOI process are also presented.
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