Ultra-low energy digital logic controller design for wireless sensor networks Public Deposited

http://ir.library.oregonstate.edu/concern/graduate_thesis_or_dissertations/st74cv675

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  • Low energy design techniques for digital circuits are examined to determine their suitability for use in a digital logic controller for wireless sensor network nodes. Transistor level simulations are used to evaluate the techniques and those demonstrating an energy reduction are used to implement a digital logic controller. The digital controller for the wireless sensor node, fabricated in a 0.18μm CMOS process, operates at 350mV while consuming 336fJ per clock cycle with a 250kbps data rate. Lab measurements show a 98% reduction in energy consumption compared to an implementation that utilizes standard design techniques, making it the lowest energy digital controller for wireless sensor nodes to date.
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  • description.provenance : Submitted by Stephen Meliza (melizas@onid.orst.edu) on 2009-04-10T22:15:40Z No. of bitstreams: 1 Meliza_MS_EE_thesis.pdf: 1832341 bytes, checksum: 45e40859e5a388a728c90f954fd9b280 (MD5)
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  • description.provenance : Approved for entry into archive by Laura Wilson(laura.wilson@oregonstate.edu) on 2009-04-23T15:28:56Z (GMT) No. of bitstreams: 1 Meliza_MS_EE_thesis.pdf: 1832341 bytes, checksum: 45e40859e5a388a728c90f954fd9b280 (MD5)
  • description.provenance : Approved for entry into archive by Julie Kurtz(julie.kurtz@oregonstate.edu) on 2009-04-15T16:28:01Z (GMT) No. of bitstreams: 1 Meliza_MS_EE_thesis.pdf: 1832341 bytes, checksum: 45e40859e5a388a728c90f954fd9b280 (MD5)

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