Design of a True-Q Flip Flop Public Deposited

http://ir.library.oregonstate.edu/concern/graduate_thesis_or_dissertations/th83m272v

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  • A CMOS implementation of a True-Q Flip Flop is presented. It can perform either as an asynchronous storage element in micropipelines or a part of the synchronizer. It is capable of double-edge triggering which latches data at both the rising and the trailing edges. It is also free of the metastability state problem. Some analog and digital circuits are incorporated with a true double-edge triggered Flip Flop (DETFF) making it a True-Q Flip Flop. A True-Q Flip Flop outputs an acknowledge signal only after the Q and NQ are stabilized. Therefore, if the proceeding stages utilize this acknowledge signal as the triggering signal, then, the value of Q from the flip flop will not be received by the next stage if Q is in a metastable state. The number of transistors used in this implementation of True-Q flip flop is 90. Due to the overhead of circuit complexity, the time delay from Request to Acknowledge signal is 6.5ns.
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  • File scanned at 300 ppi (Monochrome) using Capture Perfect 3.0.82 on a Canon DR-9080C in PDF format. CVista PdfCompressor 4.0 was used for pdf compression and textual OCR.
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  • description.provenance : Approved for entry into archive by Patricia Black(patricia.black@oregonstate.edu) on 2012-11-21T18:40:35Z (GMT) No. of bitstreams: 1 HuiHenry1995.pdf: 1623357 bytes, checksum: bf04219a882978e79eb6eda2f7d80b91 (MD5)
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  • description.provenance : Made available in DSpace on 2012-11-21T22:39:32Z (GMT). No. of bitstreams: 1 HuiHenry1995.pdf: 1623357 bytes, checksum: bf04219a882978e79eb6eda2f7d80b91 (MD5) Previous issue date: 1994-10-20

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