Performance improvement with logic-level speculation Public Deposited

http://ir.library.oregonstate.edu/concern/graduate_thesis_or_dissertations/vh53x027w

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  • Current superscalar microprocessors' performance depends on its frequency and the number of useful instructions that can be processed per cycle (IPC). Higher frequency is achieved with process advancement, new circuit techniques, and microarchitectural improvement. Number of instructions processed per cycle depends mainly on microarchitecture techniques that exploit parallelism both spatially and temporally. Most techniques employed to exploit parallelism spatially tend to increase circuit complexity and may affect the frequency thus offset the performance gain intended. Finer pipeline stages exploit parallelism temporally but may suffer reduced efficiency when there are dependencies and hazards in the long pipeline. Careful balancing between frequency and useful number of instructions processed per cycle is one of the important microprocessor design tradeoffs. In this thesis we propose a method called approximation to reduce the logic delay of a pipe-stage. The basic idea of approximation is to implement the logic function partially instead of fully. Most of the time the partial implementation gives the correct result as if the function is implemented fully but with fewer gates delay allowing a higher pipeline frequency. We apply this method on three logic blocks. Simulation results show that this method provides some performance improvement for a wide-issue superscalar if these stages are finely pipelined.
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  • description.provenance : Approved for entry into archive by Patricia Black(patricia.black@oregonstate.edu) on 2012-08-23T18:48:07Z (GMT) No. of bitstreams: 1 LiuTong2001.pdf: 2686207 bytes, checksum: 65256875aeaaa8aabd3f3de2c9342949 (MD5)
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