Graduate Thesis Or Dissertation

 

A dual-path 2-0 MASH ADC with dual digital error correction Öffentlichkeit Deposited

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https://ir.library.oregonstate.edu/concern/graduate_thesis_or_dissertations/vq27zr00v

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  • This dissertation presents a dual-path 2-0 MASH (Multi-stAge-noise -SHaping) ADC with two verified digital corrections of DAC mismatch error and quantization noise leakage. By using these two techniques, the requirements for the analog circuits are greatly relaxed. The dual-path structure generates two outputs, one only composed of conversion errors, the other input signal plus conversion errors. For the above two correlation algorithms, the input signal is the largest interference. Hence, the first output is suitable for a correlation operation, greatly speeding up the correlation based techniques, while the second serves as the final output after removal of the DAC error and quantization noise leakage. The dissertation also proposes a new Dynamic Element Matching (DEM) technique, namely Segmented Data Weighted Averaging (SeDWA), for application in a multi-bit Delta-Sigma Modulator (DSM). In SeDWA, the DAC elements are divided into several subsets with Data Weighted Averaging (DWA) applied in each set. This allows a simpler and faster implementation, and the selecting sequences for the DAC elements are more randomized than in conventional DWA. It reduces pattern tones, but still provides mismatch error shaping. In the simulated Power Spectra Density (PSD), no in-band pattern tones were observed, and only a moderate rise of the noise floor. Therefore, higher Spurious-Free Dynamic Range (SFDR) was achieved. The implementation of SeDWA can be simpler and faster than that of conventional DWA, making it suitable for high-speed applications. To verify the first technique, an experimental dual-path 2-0 MASH DSM was built. The split structure allows fast convergence and improved accuracy for the correction. Using a 20 MHz clock, the prototype chip achieved an 84 dB dynamic range in a 1.25 MHz signal band, when fabricated in CMOS 0.18um process.
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  • description.provenance : Submitted by Zhenyong Zhang (zhangzhe@onid.orst.edu) on 2006-12-17T18:00:36Z No. of bitstreams: 1 Thesis_zhenyong.pdf: 2952103 bytes, checksum: bf4134f9924f59dab059e69b45aeb9ec (MD5)
  • description.provenance : Made available in DSpace on 2007-01-08T16:53:08Z (GMT). No. of bitstreams: 1 Thesis_zhenyong.pdf: 2952103 bytes, checksum: bf4134f9924f59dab059e69b45aeb9ec (MD5)
  • description.provenance : Approved for entry into archive by Julie Kurtz(julie.kurtz@oregonstate.edu) on 2007-01-04T18:49:57Z (GMT) No. of bitstreams: 1 Thesis_zhenyong.pdf: 2952103 bytes, checksum: bf4134f9924f59dab059e69b45aeb9ec (MD5)

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