Successive-approximation-register (SAR) analog-to-digital converters are popular for medium accuracy, medium speed and low power applications, such as in biomedical applications. They have low latency and simple architecture compared with ΔΣ ADCs. This is because of SAR ADCs’ binary searching scheme. Furthermore, SAR ADCs can apply oversampling and noise shaping schemes which are used in ΔΣ ADCs. As a result, the noise-shaping SAR ADC architecture has received more and more attention as a high resolution and power efficient solution for many sensor applications. In this dissertation, novel configurations have been explored for noise-shaping SAR ADCs for power-efficient and high-accuracy data conversion.
Frist, a first-order noise-shaping (NS) SAR ADC using a two-capacitor based DAC (2-C DAC) is described and discussed. There are only two equal valued capacitors used in the DAC, so the total number of capacitors is much less than in conventional binary weighted DAC. Therefore, the 2-C DAC is good for capacitor matching. Furthermore, this 2-C DAC architecture only samples the reference once, so that the proposed NS SAR ADC doesn’t need a reference buffer on or off chip. An active integrator is implemented and used to contribute an ideal first order noise shaping effect and can be extended to second order noise shaping by adding a few extra capacitors with only one integrator. The ADC was fabricated in 180nm CMOS technology. The prototype occupies 0.25mm2. For a 2kHz signal bandwidth, it achieved 78.9dB SNDR and 87.6dB SFDR with a 32 oversampling ratio (OSR). It consumes 74.2 uW power from 1.5V power supply.
Next, a noise shaping SAR ADC with on-chip digital DAC calibration was proposed and implemented. Correlated double sampling (CDS) and correlated level shifting (CLS) are combined to implement the proposed architecture. With these two techniques, the design specifications for the op-amp used in integrator are relaxed. CDS minimized the effect of DC offset and flicker noise from the op-amp, and CLS boosted the effective DC gain of the op-amp. Therefore, the total power consumption of the op-amp can be decreased by about 50% compared with the same NS SAR ADC performance. Also, an incremental ADC (IADC) based on-chip DAC calibration scheme was proposed and implemented. The proposed calibration scheme will share all blocks in the proposed NS SAR ADC, so it will not increase the complexity of the circuitry. The calibration, it gives a more than 13dB improvement on the SNDR. The proposed ADC was fabricated in 130nm CMOS technology. It achieved 85.1 dB DR, 82.6dB SNDR and 90.9dB SFDR with 32 OSR. It consumes 40uW power from 1.6V power supply which gives a 163dB Schreier Figure of Merit.