Dynamically configurable systolic arrays Public Deposited

http://ir.library.oregonstate.edu/concern/graduate_thesis_or_dissertations/w95053617

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  • Digital signal and image processing and other real time applications involve simple but large amounts of computations. These problems have an enormous amount of inherent parallelism and demand high speed computation. Conventional computers do not possess these characteristics and this had led to the development of new architectural concepts. Among the new architectures, the systolic and wavefront arrays processors have gained a lot of attention because of their high processing bandwidth. The systolic arrays combine massive pipelining with parallelism. There is one problem with this approach of designing application specific chips wherein each of these chips is capable of processing a single algorithm. A number of real time applications require more than one algorithm to be executed for a complete solution. . One solution to the above problem is to develop reconfigurable array structures. One notable proposal is the Confiurable Highly Parallel Computer (CHiP) which is capable of reconfiguring the array to suit different interconnection schemes. In this thesis, the CHiP has been adapted to suit a family of systolic architectures. The dynamically Configurable Systolic Array proposed is designed to accommodate the linear configuration to solve convolution and polynomial multiplication, a square configuration to solve full matrix multiplication and a hexagonal array for band matrix multiplication. The array is a 2-dimensional array arranged in a square grid and functions as an attached processor to a host. Each processor in the array is connected only to it's immediate neighbours and all external communication is only through the edge processors. The actual interconnection patterns are implemented by a set of tristate drivers that are part of the communication links between neighbouring processors. The drivers are controlled by the controller and patterns are determined by the control signals generated. The arithmetic unit is a simple multiplier along with an adder capable of executing the inner product computation common to many signal and image processing applications. The array has been built on a Genesil Silicon Compiler using 2-micron CMOS technology. The three array configurations have been successfully simulated and tested. The algorithms have been executed in times that closely match the theoretical times. More importantly, the feasibility of building a single chip to implement a number of algorithms has been demonstrated and paves the way for further research in this area.
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