Power Efficient Hybrid Architecture for High Resolution Analog-to-Digital Converters Public Deposited

http://ir.library.oregonstate.edu/concern/graduate_thesis_or_dissertations/x059cd380

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  • Analog-to-digital converters (ADCs) are the key building block for sensor applications, such as wireless communications and digital electronics. These applications require ADCs to have medium to high accuracy (normally from 10-14 bits) and relatively low signal bandwidth (ranging from 100Hz-150kHz). Since these applications are often powered by batteries, high power efficiency of the ADCs is one of the biggest challenges of the design. Recently, noise-shaping SAR ADCs have been used inside of a delta-sigma modulator to achieve relatively high resolution while maintaining excellent power efficiency. However, the passive noise shaping from the SAR ADC can cause low frequency quantization noise leakage, which degrades the ADC accuracy. Additionally, the maximum noise shaping order has been limited to second order in reported passive noise shaping SAR ADC works. To achieve a higher order noise transfer function (NTF) and reduce the in-band quantization noise leakage, a single opamp-based third-order delta-sigma modulator with a 4-bit noise-shaping SAR quantizer is proposed in this work. Designed with a 65nm CMOS technology, the simulated prototype modulator attains 84.5dB SNDR over 50kHz signal bandwidth sampled at 3.2MH. The power consumption of the ADC is 50.7μW. The simulation results demonstrate the power efficiency of the proposed modulator for sensor network and portable device applications.
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