Design methodology for low-jitter phase-locked loops Public Deposited

http://ir.library.oregonstate.edu/concern/graduate_thesis_or_dissertations/xg94ht415

Descriptions

Attribute NameValues
Creator
Abstract or Summary
  • This thesis presents a systematic top-down methodology for simulating a phase-locked loop using a macro model in Verilog-A. The macromodel has been used to evaluate the jitter due to supply noise, thermal noise, and ground bounce. The noise simulation with the behavioral model is roughly 310 times faster (best case) and 125 times faster (worst case). The accuracy of the model depends on the accurate evaluation of the non-linear transfer function from the various noisy nodes to the output. By modeling the noise transfer function of the circuit as closely as possible, 100% accuracy for the behavioral noise simulations compared with the HSPICE noise simulations is obtained. The macro model is written for a charge-pump phase-locked loop, but can be easily extended to other architectures. The simulations are completed using SpectreS in Cadence. The designer can use the model to estimate the jitter at the output of the PLL in a top-down design methodology or cross verify the performance of an existing chip in a bottom-up approach.
Resource Type
Date Available
Date Copyright
Date Issued
Degree Level
Degree Name
Degree Field
Degree Grantor
Commencement Year
Advisor
Committee Member
Academic Affiliation
Non-Academic Affiliation
Subject
Rights Statement
Peer Reviewed
Language
Digitization Specifications
  • File scanned at 300 ppi (Monochrome) using ScandAll PRO 1.8.1 on a Fi-6770A in PDF format. CVista PdfCompressor 4.0 was used for pdf compression and textual OCR.
Replaces
Additional Information
  • description.provenance : Approved for entry into archive by Patricia Black(patricia.black@oregonstate.edu) on 2012-08-22T20:34:20Z (GMT) No. of bitstreams: 1 BhagavatheeswaranShanthiS2001.pdf: 566618 bytes, checksum: 27398f3c0bc72df636de74ba3f85a8ab (MD5)
  • description.provenance : Made available in DSpace on 2012-08-22T20:36:04Z (GMT). No. of bitstreams: 1 BhagavatheeswaranShanthiS2001.pdf: 566618 bytes, checksum: 27398f3c0bc72df636de74ba3f85a8ab (MD5) Previous issue date: 2001-02-23
  • description.provenance : Approved for entry into archive by Patricia Black(patricia.black@oregonstate.edu) on 2012-08-22T20:36:04Z (GMT) No. of bitstreams: 1 BhagavatheeswaranShanthiS2001.pdf: 566618 bytes, checksum: 27398f3c0bc72df636de74ba3f85a8ab (MD5)
  • description.provenance : Submitted by Kaylee Patterson (kdpscanner@gmail.com) on 2012-08-22T16:32:39Z No. of bitstreams: 1 BhagavatheeswaranShanthiS2001.pdf: 566618 bytes, checksum: 27398f3c0bc72df636de74ba3f85a8ab (MD5)

Relationships

Parents:

This work has no parents.

Last modified

Downloadable Content

Download PDF

Items