Graduate Thesis Or Dissertation
 

Simulation and modeling of substrate noise generation from synchronous and asynchronous digital logic circuits

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https://ir.library.oregonstate.edu/concern/graduate_thesis_or_dissertations/zs25xd80h

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  • Efficient methods for simulating the substrate noise generated by complex synchronous and asynchronous digital logic circuits are presented. By simulating digital logic at the gate level, and precharacterizing the gates, the substrate noise generation can be predicted and used in a transistor level simulation of the sensitive analog blocks. This approach is shown to have better than 20 percent peak-to-peak matching for both traditional CMOS logic and NULL Convention Logic (NCL) by correctly modeling critical gate characteristics. Synchronous and asynchronous versions of a pseudo-random number generator (PRNG) are implemented in a 0.25um CMOS test chip. Simulations validate both a standard transistor level setup and the predictive substrate noise approach against measurements. Simulations of an 8051 processor, with separate synchronous and asynchronous logic cores, are in good agreement with measurements from another 0.25um CMOS test chip, and show validation with a large and complex circuit.
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