Honors College Thesis


A Study of Sample-and-Hold Circuit with Application to Beat Test and Dual-Slope ADC Public Deposited

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  • This undergraduate thesis provides an overview on analyzing and designing open-loop sampleand- hold (S/H) circuits. It also describes a technique used to verify functions of an S/H circuit known as beat frequency test, as well as an application of S/H circuit, a dual-slope integrating analog-to-digital (A/D) converter. The first section focuses the fundamentals of S/H circuit, its theory of operation and its deviations from the ideal response. Charge injection and bandwidth limitation are the two major problems associated with an open-loop S/H circuit. The next section explains principles behind the beat test, its system setup, and the approach for designing the S/H circuit in a beat frequency test from plotting the major design parameters. A/D converter’s fundamentals are introduced, followed by a survey on the system architecture and the analog components inside a dual-slope integrating A/D converter. Computer simulations of the S/H circuits and the measured results from the fabricated monolithic S/H circuits are also presented.
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