Design of a Process Independent Tool for the Creation of On-Chip Serial Test Interfaces Public

http://ir.library.oregonstate.edu/concern/honors_college_theses/ff365721j

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  • The push towards higher performing and more sensitive mixed signal circuitry has required the parallel development of increasingly more complex and sensitive test and calibration harnesses. Current off-chip methods of test and calibration may require higher pin counts or induce unwanted parasitic interference. In this thesis, the design of a process independent tool for the creation of on-chip serial test interfaces is presented. This tool is part of a complete on-chip calibration solution designed by the author and his group for use in mixed signal integrated circuits. The system accomplishes several goals reducing pin count, minimizing parasitic interference, and facilitating test automation for the calibration and test harnesses by moving the test harness onto the die of the mixed signal integrated circuit. The tool presented in this paper was designed with the goals of easing test harness implementation, facilitating multiple fabrication processes, and providing flexibility to the chip designer. A set of serial test interfaces generated by the tool was fabricated in a 0.5um CMOS process in order to verify the both tool and its output.
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