Honors College Thesis
 

Design of a Process Independent Tool for the Creation of On-Chip Serial Test Interfaces

公开 Deposited

可下载的内容

下载PDF文件
https://ir.library.oregonstate.edu/concern/honors_college_theses/ff365721j

Descriptions

Attribute NameValues
Creator
Abstract
  • The push towards higher performing and more sensitive mixed signal circuitry has required the parallel development of increasingly more complex and sensitive test and calibration harnesses. Current off-chip methods of test and calibration may require higher pin counts or induce unwanted parasitic interference. In this thesis, the design of a process independent tool for the creation of on-chip serial test interfaces is presented. This tool is part of a complete on-chip calibration solution designed by the author and his group for use in mixed signal integrated circuits. The system accomplishes several goals reducing pin count, minimizing parasitic interference, and facilitating test automation for the calibration and test harnesses by moving the test harness onto the die of the mixed signal integrated circuit. The tool presented in this paper was designed with the goals of easing test harness implementation, facilitating multiple fabrication processes, and providing flexibility to the chip designer. A set of serial test interfaces generated by the tool was fabricated in a 0.5um CMOS process in order to verify the both tool and its output.
License
Resource Type
Date Available
Date Issued
Degree Level
Degree Name
Degree Field
Degree Grantor
Commencement Year
Advisor
Non-Academic Affiliation
权利声明
Publisher
Peer Reviewed
Language
Replaces

关联

Parents:

This work has no parents.

属于 Collection:

单件

缩略图 标题 上传日期 公开度 行动
file details edmonds_thesis.pdf 2017-07-29 公开 下载