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A DAC and comparator for a 100MHz decision feedback equalization loop

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dc.contributor.advisor Kenney, John G.
dc.creator Engelbrecht, Linda M.
dc.date.accessioned 2012-10-08T20:46:37Z
dc.date.available 2012-10-08T20:46:37Z
dc.date.copyright 1996-09-05
dc.date.issued 1996-09-05
dc.identifier.uri http://hdl.handle.net/1957/34236
dc.description Graduation date: 1997 en_US
dc.description.abstract Decision Feedback Equalization (DFE) in a data recovery channel filters the bit decision in the current symbol period in generating the sample at the comparator in the subsequent clock period. The operations of sampling, comparing, filtering the decision bits into a feedback signal, and subtraction of that feedback signal are cascaded, thereby establishing the critical timing path. Thus, this system, though simple, requires its components to have large bandwidths in order to achieve the high-speed response necessary to perform the described feedback function. For the entire system to run at speeds comparable to those of competing technologies (100MHz to 250MHz), the components must have bandwidths greater than 100MHz, and work together to provide a loop bandwidth of at least 100MHz. A 300MHz latching comparator and a 125MHz 6-bit current-DAC were designed in a 5V, 1 um CMOS n-well process for use in a DFE loop. Both blocks are fully differential and achieve an accuracy of 1/2 LSB (10uA) over a differential signal range of 1.28mA. This is true for their operations at speed, in isolated simulation and as contiguous blocks. The DAC power consumption is relatively high at 23mW, due to internal switching circuits which require a static current, but the comparator's power consumption is minimal at 5mW. en_US
dc.language.iso en_US en_US
dc.subject.lcsh Feedback control systems en_US
dc.subject.lcsh Digital-to-analog converters en_US
dc.title A DAC and comparator for a 100MHz decision feedback equalization loop en_US
dc.type Thesis/Dissertation en_US
dc.degree.name Master of Science (M.S.) in Electrical and Computer Engineering en_US
dc.degree.level Master's en_US
dc.degree.discipline Engineering en_US
dc.degree.grantor Oregon State University en_US
dc.description.digitization File scanned at 300 ppi (Monochrome, 8-bit Grayscale) using ScandAll PRO 1.8.1 on a Fi-6670 in PDF format. CVista PdfCompressor 4.0 was used for pdf compression and textual OCR. en_US
dc.description.peerreview no en_us

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