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Zinc tin oxide thin-film transistor circuits

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dc.contributor.advisor Wager, John
dc.creator Heineck, Daniel Philip
dc.date.accessioned 2008-12-23T23:05:32Z
dc.date.available 2008-12-23T23:05:32Z
dc.date.copyright 2008-12-10
dc.date.issued 2008-12-23T23:05:32Z
dc.identifier.uri http://hdl.handle.net/1957/9975
dc.description Graduation date: 2009 en_US
dc.description.abstract The primary objective of this thesis is to develop a process for fabricating integrated circuits based on thin-film transistors (TFTs) using zinc tin oxide (ZTO) as the channel layer. ZTO, in contrast to indium- or gallium-based amorphous oxide semiconductors (AOS), is perceived to be a more commercially viable AOS choice due to its low cost and ability to be deposited via DC reactive sputtering. In the absence of an acceptable ZTO wet etch process, a plasma-etching process using Ar/CH₄ is developed for both 1:1 and 2:1 ZTO compositions. An Ar/CH₄ plasma etch process is also designed for indium gallium oxide (IGO), indium gallium zinc oxide (IGZO), and indium tin oxide (ITO). Ar/CH₄ dry etches have excellent selectivity with respect to SiO₂, providing a route for obtaining patterned ZTO channels. A critical asset of ZTO process integration involves removing polymer deposits after ZTO etching without active layer damage. A ZTO process is developed for the fabrication of integrated circuits which use ZTO channel enhancement-mode TFTs. Such ZTO TFTs exhibit incremental and average mobilities of 23 and 18 cm²V⁻¹s⁻¹, respectively, turn-on voltages approximately 0 to 1.5 V and subthreshold swings below 0.5 V/dec when annealed in air at 400 °C for 1 hour. Several types of ZTO TFT circuits are realized for the first time. Despite large parasitic capacitances due to large gate-source and gate-drain overlaps, AC/DC rectifiers are fabricated and found to operate in the MHz range. Thus, they are usable for RFID and other equivalent-speed applications. Finally, a ZTO process for simultaneously fabricating both enhancement-mode and depletion-mode TFTs on a single substrate using a single target and anneal step is developed. This dual-channel process is used to build a high-gain two-transistor enhancement/depletion inverter. At a rail voltage of 10 V, this inverter has a gain of 10.6 V/V, the highest yet reported for an AOS-based inverter. This E/D inverter is an important new functional block which will enable the realization of more complex digital logic circuits. en_US
dc.language.iso en_US en_US
dc.subject zinc tin oxide en_US
dc.subject thin film transistors en_US
dc.subject enhancement/depletion inverter en_US
dc.subject amorphous oxide semiconductors en_US
dc.subject ac/dc rectifier en_US
dc.subject.lcsh Thin film transistors en_US
dc.subject.lcsh Amorphous semiconductors en_US
dc.subject.lcsh Zinc oxide thin films en_US
dc.subject.lcsh Integrated circuits -- Design and construction en_US
dc.title Zinc tin oxide thin-film transistor circuits en_US
dc.type Thesis en_US
dc.degree.name Master of Science (M.S.) in Electrical and Computer Engineering en_US
dc.degree.level Master's en_US
dc.degree.discipline Engineering en_US
dc.degree.grantor Oregon State University en_US
dc.contributor.committeemember Conley, John F. Jr
dc.contributor.committeemember Keszler, Douglas
dc.contributor.committeemember Warnes, William


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