This thesis describes the adder to be used with the Galaxy computer, which is to be constructed at Oregon State University.
The need for faster, more reliable adders is discussed
along with previous adder designs related to the
Galaxy Fast Carry Adder.
Both the logical design and circuit design of...
The concept of combining arithmetic and memory capability on
a single semiconductor chip has become practical from a system's
viewpoint through the decreased cost of semiconductor memories and
high circuit densities achieved through large scale integration. This
paper describes a model for studying the feasibility of such systems.
An arithmetic-memory...
Research in digital computers takes two paths: one uses the
computer as a tool to reach certain objectives; on the other, the computer
itself is the object of research. The NEBULA computer was
built with the latter in mind. The system design and logical design
are described here in detail....
Multi-level decision feedback equalization (MDFE) is an effective sampled signal processing technique to remove inter-symbol interference (ISI) from disk read-back signals. Parallelism which doubles the symbol rate can be realized by utilizing the characteristic of channel response and decision feedback equalization algorithm.
A mixed-signal IC implementation has been chosen for...
Multi-stage delta-sigma (ΔΣ) architectures, commonly known as MASH, are the preferred choice for analog-to-digital converters (ADCs) used in broadband communication applications, where high-resolution (above 14 bits) and high-bandwidth (several MHz) performances are required. Current state-of-the-art designs are capable of as much as 5-MS/s output data rates with 90-dB SNR. However,...
Enabled by continued device scaling in CMOS technology, more and more functions that were previously realized in separate chips are getting integrated on a single chip nowadays. Integration on silicon has opened the door to new portable wireless applications, and initiated a widespread use of these devices in our common...
Delta-Sigma (ΔΣ) analog-to-digital converters (ADCs) are widely used in wireless transceivers. Recently, continuous-time (CT) ΔΣ ADCs gain growing interest in wireless applications for their lower power consumption and wider input bandwidth as compared with the discrete-time (DT) counterparts.
In this thesis, a wideband low-power CT ΔΣ modulator for next generation...
In recent years, there has been growing interest in both industry and academia to use continuous-time (CT) Δ-Σ A/D converters for wideband wireless and wireline communication applications.
So far no reported CT Δ-Σ A/D modulator achieves 14-bit or higher dynamic range (DR) with more than 2MHz signal bandwidth (equivalently 4MS/s)....
Scaling of CMOS technology has progressed relentlessly for the past several
decades. In order for this unprecedented scaling to benefit the performance of
large digital systems, the communication bandwidth between integrated circuits
(ICs) must scale accordingly. However, interconnect technology does not scale as
aggressively, making communication between chips the major...
The counterflow pipeline concept was originated by Sproull and Sutherland to demonstrate
the concept of asynchronous circuits. This architecture relies on distributed decision
making and localized clocking and data movement. We have taken these ideas and reformulated
them into a substantially faster more scalable architecture that has the same distributed...
Low-distortion architecture is widely used in wideband discrete-time switched-capacitor delta-sigma ADC design. However, it suffers from the power-hungry active adder and critical timing for quantization and dynamic element matching (DEM). To solve this problem, this dissertation presents a delta-sigma modulator architecture with shifted loop delays. In this project, shifted loop...
In this thesis, a novel Direct-Charge-Transfer (DCT) integrator structure is proposed, which can settle much faster than regular switch-capacitor integrators. A new Spread-Spectrum Dynamic Element Matching (SS-DEM) algorithm is also introduced, which can effectively spread or shape the nonlinearity error of multi-bit DAC in the feedback path, thus improve the...
Advances in electronic systems have lead to the demand for high resolution, high bandwidth Analog-to-Digital Converters (ADCs). Oversampled ADCs are well- known for high accuracy applications since they benefit from noise shaping and they usually do not need highly accurate components. However, as a consequence of oversampling, they have limited...
Recently, delta-sigma modulation has become a widely applied technique for high-performance analog-to-digital conversion of narrow-band signals. Most of the early designs used discrete-time structure for good accuracy and good linearity. The transfer functions are independent of the clock frequency. However, high unity-gain bandwidths of the opamps are required to satisfy...
Sensors find a variety of applications in portable electronics, automotive and biomedical solutions. The demand for low power and high dynamic range makes the design of digital sensor readout circuits quite challenging. Traditionally, these circuits are realized using amplifiers with passive feedback or precision analog comparators which are power hungry...
This dissertation presents an incremental analog-to-digital converter (ADC) with digital digital-to-analog converter (DAC) mismatch correction. A theoretical time-domain analysis technique was developed to predict the noise performance of the incremental ADC, and a new optimization technique was proposed to minimize the output noise.
In the calibration mode, the incremental ADC...
The most accurate method for performing analog signal processing in MOS (metal-oxide-semiconductor) integrated circuits is through the use of switched-capacitor circuits. A switched-capacitor circuit operates as a discrete-time signal processor. These circuits have been used in a variety of applications, such as filters, gain stages, voltage-controlled oscillators, and modulators. A...
Delta-Sigma (ΔΣ) analog-to-digital converters (ADCs) are traditionally used in high quality audio systems, instrumentation and measurement (I&M) and biomedical devices. With the continued downscaling of CMOS technology, they are becoming popular in wideband applications such as wireless and wired communication systems,high-definition television and radar systems. There are two general realizations...
VCO-based ADCs have recently emerged as attractive alternative to conventional DeltaSigma (ΔΣ) modulator architectures. Few salient features of a VCObased ADC are: 1) the quantization noise is 1st order noise shaped, 2) it is an open loop architecture, and, 3) its implementation is mostly digital in nature. Hence, they are...
For today’s ubiquitous portable devices, innovative integrated circuits with high performance
yet very low power are necessary. As these devices are used to communicate and sense real world signals in the environment, analog-to-digital converters (ADC) and systems are the key interface circuits needed to digitize the sensed information and they...
Decision feedback equalization (DFE) is a sampled-data technique used for data recovery in digital communications channels. Multi-level decision feedback equalization (MDFE) has been developed for channels using the 2/3(1,7) RLL code.
The optimum detector for a digital communication channel affected by ISI and noise consists of a matched filter, followed...
This thesis discusses a special type of a versatile, distributed control system, the Taskmaster II. It includes a detailed specification of a readily realizable Taskmaster system utilizing a layered communication among units, oriented on the ISO OSI seven layer model. The specification was developed from the analysis of previous research...
This thesis describes circuit architectures and techniques that facilitate the
automatic synthesis and fabrication of analog-to-digital converters (ADCs). Since
automated synthesis already exists for digital circuits and is part of the digital
circuit design flow, this work demonstrates the feasibility of ADC synthesis with
little or no modification to presently...
Several papers propose the use of on-line arithmetic for signal processing applications implemented on FPGAs. Although those papers provide reasonable arguments for the use of on-line arithmetic, they give only inadequate or incomplete comparisons of the proposed on-line designs to other state of the art solutions on FPGAs. In this...
A procedure for automating the design and layout of analog-to-digital converters (ADCs) is presented. This procedure makes use of the existing synthesis and place-and-route tools that are common in digital circuit design. A method for adding rudimentary analog cells to the standard library is described, allowing the designer to synthesize...
Incremental ADCs (IADCs) have many advantages for low-frequency high-accuracy data conversion—they are easy to multiplex between channels, need simpler digital decimation filter, and allow extended counting with a Nyquist-rate ADC. A single-loop incremental ADC was designed and fabricated in 90 nm for a biosensor interface circuit. It incorporates one integrator,...
Due to advances in high-density low-cost VLSI and communication technology,
digital filtering and signal processing are being widely used for real-time signal processing
applications. Given the filter specification, choosing the best filter structure for a given
application is not a trivial task. The choice of a particular filter structure depends...
The objective of this thesis is to design a high speed digital FIR filter. The inputs of the
system come from a Delta-Sigma modulator. This FIR filter takes 1024 inputs,
multiplies them with their coefficients and adds the results. The main design task is to
take the input data, which...
In this dissertation, a new Δ∑ A/D converter is presented that is ideally suited for communication applications. It is based on a single-loop single-stage structure, which can realize a high maximum out-of-band quantization noise gain while maintaining stable operation and thus achieve 14-bit resolution at 8 times oversampling. A fifth-order...
In this thesis work, a design of 14-bit, 20MS/s segmented digital-to-analog converter (DAC) is presented. The segmented DAC uses switched-capacitor configuration to implement 8 (LSB) + 6 (MSB) segmented architecture to achieve high performance for minimum area. The implemented LSB DAC is based on quasi-passive pipelined DAC that has been...
This thesis proposes a novel technique for the design of pipelined and cyclic ADCs utilizing generalized radix gain stages. Several models have been proposed for the optimization of high performance pipelined ADCs by various researchers. This work builds upon them, using a simple but accurate model to estimate the optimal...
Digital-to-analog converters (DACs) with wide dynamic range and high
linearity are required for high-end audio applications. A multi-bit delta sigma
audio DAC, using a novel gain-correction technique, is described in this thesis. For
widely varying on-chip RC time constant, the DAC gain can be accurately
controlled by the correction circuitry....
With the ever-increasing demand for portable devices used in applications
such as wireless communication, mobile computing, consumer electronics, etc.,
the scaling of the CMOS process to deep submicron dimensions becomes more
important to achieve low-cost, low-power and high-performance digital systems.
However, this downscaling also requires similar shrinking of the supply...
Delta-Sigma Modulator-based Analog-to-Digital converter design is an active area of research. New topologies require extensive simulations to verify their performance. A series of improvements were made to an existing circuit simulation package in order to speed the simulation process for the designer. Various examples of these improvements are presented in...
This dissertation presents a low-power high-resolution delta-sigma ADC. Two new architectural design techniques are proposed to reduce the power dissipation of the ADC. Compared to the conventional active adder, the direct charge transfer (DCT) adder greatly saves power by keeping the feedback factor of the active adder unity. However, the...
A new circuit technique called Folded Source Coupled Logic (FSCL) has been developed
to implement the digital section of mixed-signal IC applications. This FSCL circuit technique
offers the advantage of low overlap current spikes during the switching transitions
of conventional CMOS gates. This overlap current spike has become one of...
Computers have made a great contribution to the
design process in various applications, such as design
analysis and simulation. A new technology called
Computer-aided design (CAD) has helped the designer to
design and build very intricate systems.
While most of CAD software is run on workstations or
microcomputers with one...
Data converters are ubiquitous building blocks of a signal chain. The rapid increase in
communication and connectivity devices presents new avenues for pushing the state of
the art analog to digital converters. Techniques for improving resolution, bandwidth,
linearity and bit-error rate, while reducing the power, energy and area is the...
The release of the IEEE802.15.6 standard has led to increased interest in low-power technologies for wireless body-area-networks (WBANs). The power dissipation, supply voltage, and die area are some of the most important criteria for successful WBAN implementations. Digital-intensive RX architectures can potentially result in sub-1V operation with significant reductions in...
This dissertation investigates diverse techniques to support multithreading in modern high performance processors. The mechanisms studied expand the architecture of a high performance superscalar processor to control efficiently the interaction between software-controlled and hardware-controlled multithreading. Additionally, dynamic speculative mechanisms are proposed to exploit thread-level-parallelism (TLP) and instruction-level-parallelism (ILP) on a...
Metal-plate-connected (MPC) trusses have traditionally been designed based on a
tributary load distribution and a simplified truss model. This design method ignores the
load-sharing and composite action in MPC roof truss systems, the semi-rigidity of MPC
joints, and joint eccentricity.
The main objective of this study was to provide a...
This dissertation presents two high-speed pipeline successive approximation analog-to-digital converters (SAR ADCs). Capacitive DACs and resistive DACs are utilized in these two pipeline SAR ADCs, respectively.
The pipeline SAR ADC with capacitive DACs can save 50% switching power compared with other time-interleaved SAR ADCs since the total capacitance of the...
Ultra-high-speed (>10GS/s), medium-resolution (5~6bit), low-power (<50mW) analog-to-digital converter can find it application in the areas of digital oscilloscopes and next-generation serial link receivers. There are several challenges to enable a successful design, however. First, the time-interleaved architecture is required in order to achieve over 10GS/s sampling rate, with the trade-off...
A new structure for the implementation of bit/serial adaptive IIR filter is
presented. The bit level system consists of gated full adders for the arithmetic
unit and data latches for the data path. This approach allows recursive
operation of the IIR filter to be implemented without any global
interconnections, minimal...
This thesis presents a novel algorithmic A/D converter to be used in a biosensor. The converter is capable of a conversion rate of 1.5 bits/phase and hence the required conversion time is reduced. The proposed architecture is analyzed for non-ideal effects and compared with existing algorithmic A/D architectures. The converter...
Multi-Gigahertz sampling rate Analog-to-Digital Converters (ADC) with 5-8 bits resolution are used in many signal communication applications. Unfortunately, the performance of the high speed ADC is limited by the timing accuracy of the sampling clock. A small sampling uncertainty can cause a large error in the sampled voltage and result...
Continuous process scale-down and emerging markets for low-power/low-voltage mobile systems call for low-voltage analog integrated circuits. Switched-capacitor circuits are the building blocks for analog signal processing and will encounter severe overdrive problems when operating at low-voltage conditions. There are several well-known techniques to bypass the problem. These approaches include: (1)...
Low energy design techniques for digital circuits are examined to determine their suitability for use in a digital logic controller for wireless sensor network nodes. Transistor level simulations are used to evaluate the techniques and those demonstrating an energy reduction are used to implement a digital logic controller. The digital...
The exponential rate of advances in modern communication devices in the last several years have brought us higher levels of functionality and performance as well as reductions in physical size and power consumption. To continue this rate of advancement, next generation systems require wider bandwidth and higher resolution ADCs. Additionally,...
A digital phase locked loop (DPLL) and a statistical time-to-digital converter (STDC) were previously fabricated in a 0.35µm, 3.3V SOI CMOS process. This work summarizes these designs and characterizes the measured performance. Simulations supplement the measurements where applicable.
The DPLL was found to reach a locked state under a limited...
The demand for portable electronic systems and the continued
down-scaling of device dimensions resulted in rapid improvement in
the performance of integrated systems. Several low-voltage design
techniques have been proposed to operate analog circuits with sub-1V
supply. However, these techniques require higher power consumption
to achieve large dynamic range while...
Oregon State University Libraries and Press (OSULP) has a long history of digitizing, creating, and curating digital objects. These objects include digital representations of unique items from the Special Collections and Archives Research Center (SCARC) such as the photographs, maps, manuscripts, audio, and video housed in Oregon Digital. The ScholarsArchive@OSU...
With the growing demand for portable/consumer electronics, such as digital
audio/video (AV), the downscaling of device dimensions, which enables the
integration of an increasing number of transistors in a single chip, is mandatory.
This trend also continuously pushes the power supply voltage down to reduce the
power consumption and improve...
Decision feedback equalizer (DFE) is an effective method to remove inter-symbol
interference (ISI) from a disk-drive read channel. Analog IC implementations of DFE
potentially offers higher speed, smaller die area, and lower power consumption when
compared to their digital counterparts.
Most of the available DFE equalizers were realized by using...
Multi-level decision feedback equalization (MDFE) is an effective technique to remove inter-symbol interference (ISI) from disk readback signals, which uses the simple architecture of decision feedback equalization. Parallelism which doubles the symbol rate can be realized by setting the first tap of the feedback filter to zero.
A mixed-signal implementation...
A comprehensive and scalable solution for high-performance switched capacitor amplification is presented. Central to this discussion is the concept of ring amplification. A ring amplifier is a small modular amplifier derived from a ring oscillator that naturally embodies all the essential elements of scalability. It can amplify with accurate rail-to-rail...
The focus of this thesis involves development of highly transparent, n-channel, accumulation- mode thin-film transistors employing a zinc tin oxide (ZTO) channel layer. ZTO-based transparent thin-film transistors (TTFTs) show improved device performance compared to ZnO-based TTFTs. An estimated peak effective mobility for these devices as high as ~100 cm² V⁻¹sec⁻¹...
Switched-capacitor (SC) circuits are commonly used for analog signal processing because they can be used to realize precision filters and data converters on an integrated circuit (IC). However, for high speed applications SC circuit operating speeds are limited by the internally-compensated opamps found in SC integrators, a common building block...
Harvesting energy from the environment for powering micro-power devices have been increasing in popularity. These types of devices can be used in embedded applications or in sensor networks where battery replacement is impractical. In this dissertation, different methods of energy harvesting from the environment are explored as alternative sources of...
This dissertation investigates the constraints which arise when switched-capacitor
(SC) delta-sigma modulators are designed for low-voltage operation, targeting also low
power dissipation, and proposes methods of improving the performance and optimizing
for low power dissipation. This is accomplished by identifying critical elements whose
performance can lead to increased power dissipation,...
This document describes the design and deployment of a first generation water vapor density sensing unit, the HumiSense. This device is based on an open, air-filled capacitor which is part of a resonant circuit. The frequency of the resonant circuit mixed with a fixed frequency oscillator is the basis of...
Ultra-wideband (UWB) radio is the transmission of data using an extremely wide bandwidth and very low power spectral density. In this thesis, the mereits and challenges of UWB architectures versus conventional narrowband architectures will be compared. Pulsed UWB systems can be implemented with very simple architectures. These advantages make UWB...
The objective of this thesis is to describe the design and
implementation of a VSLI reduced instruction set computer (RISC).
The RISC machine constitutes a new style of computer architecture.
It differs significantly from the complex instruction set computer
architectures (CISC) of the past. RISC architectures are
characterized by their...
Incremental ADCs (IADCs) have found wide applications in sensor interface circuitry since, compared to ∆Σ ADCs, they provide low-latency high-accuracy conversion and easy multiplexing among multiple channels. On the other hand, continuous-time ∆Σ ADCs (CTDSM) have been receiving more and more attention as a power-efficient solution in targeting medium to...
Analog-to-Digital Data Converters (ADCs) used in instrumentation and measurements often require high absolute accuracy, including excellent linearity and negligible dc offset. Incremental data converters (IDCs) provide a solution for such measurement applications. Since IDCs are essentially delta-sigma converters with reset operation before each conversion, they retain most of the advantages...
The objective of this thesis is to provide an initial demonstration of the feasibility of constructing highly transparent active electronic devices. Such a demonstration is successfully achieved in the fabrication of ZnO-based thin film transistors (TFTs) exhibiting transparency greater than ~90% in the visible portion of the electromagnetic spectrum and...
Power optimization becomes more and more important due to the design cost and reliability. Sometimes high power consumption means expensive package cost and low reliability. The first step in optimizing power consumption is determining where power is consumed within a processor. While system-level code tracing and bit transition calculation are...
This thesis explores the implementation of learning based control with predictive cruise control and the potential this technology has for increasing fuel efficiency while keeping on a well maintained schedule for commercial trucks. Traditional cruise control is wasteful when maintaining a constant velocity over rolling hills. Predictive cruise control is...
A key application of microchannel process technology (MPT) is its implementation in heat exchanger devices, since a larger surface contact area can be realized than in conventional approaches, thus achieving high heat transfer efficiency. To justify high volume production of configurations validated as prototypes, and to select from among the...
fIndoor wireless local area networks (LAN's) and personal area networks (PAN’s) have evolved very rapidly in the recent past. The indoor wireless LAN's are mainly dominated by narrow-band technologies like the IEEE 802.11a,b which are short range and provide data rates of 1 Mbps to 54 Mbps. The Bluetooth has...
A new technique is developed to recover elemental tellurium (Te) from cadmium telluride (CdTe) which is abundantly available in photovoltaic semiconductor waste. The method is based on microchannel fluid flow with the use of a supported liquid membrane (SLM) between the donor (feed) and acceptor (strip) channels. A predictive theoretical...
An enhanced swing differential Colpitts VCO (ESDC-VCO) dramatically improves
the swing of a Colpitts VCO by allowing the signal to swing below ground and above the
supply voltage. Fabricated in a 1P8M 0.13 um CMOS process, the ESDC-VCO operates
at 4.9GHz with a 0.475-V supply and consumes 2.7mW. The measured...
Low-Density Parity-check (LDPC) codes have attracted considerable attention due to their capacity approaching performance over AWGN channel and highly parallelizable decoding schemes. They have been considered in a variety of industry standards for the next generation communication systems. In general, LDPC codes achieve outstanding performance with large codeword lengths (e.g.,...
Interest in personal computer networks has grown
rapidly in recent years. As the personal computer
becomes more and more popular, implementing computer
networks on those small computers has become an
interesting topic. Such networks are usually inexpensive
and can be easily installed and maintained.
In this thesis work, CLASSLAN, such...
Minimizing the dynamic power consumption of a circuit is becoming a more and more important issue for digital circuit design in the age of portable electronics. Among all the arithmetic circuits, addition is the most fundamental operation. Therefore, designing low power adder is an important and necessary research area.
In...
The Brushless Doubly Fed Machine (BDFM) is receiving attention as a candidate for use in adjustable speed drives (ASDs) and variable speed generators (VSGs). With a large percentage of a drive or generator system's cost due to power electronics content, considerable research has been conducted to find drives in which...
The advent of superior power semiconductor devices and converter topologies
has renewed interest in ac drive systems. Although considerable research efforts have
gone into improving power electronic converter devices and topologies, very little has
been reported on the overall performance optimization of induction machine drive
systems. The report of the...
This thesis presents algorithms and tools for the automated design of RF LC CMOS voltage controlled oscillators (VCOs) with low phase noise given a set of specifications. The electromagnetic solver, ASITIC, combined with the circuit simulator, SpectreRF, allows optimization of the VCO circuit parameters and inductor layout. This approach gives...
A generalized, three-dimensional, finite element bridge model was created in order to efficiently and accurately assess live-load girder distribution factors for a variety of bridge types. This model shortens the time required by bridge analysts to develop individual finite element models for bridges of varying geometries. The creation of the...
In modern telecommunication applications, the need for high-reliability and high data rate is important because of factors such as a higher demand in multimedia capability of mobile devices and the exponentially increasing number of subscribers. Wireless communications in today’s technology have many limitations due to channel imperfections, which result in...
The transition from second-generation (2G) to third-generation (3G) wireless cellular and cordless telephone systems requires multi-standard adaptability in a single RF receiver equipment. An important answer to this request is the use of Delta-Sigma modulators for IF-to-baseband conversion, which will satisfy the dynamic range requirements for digital signal processing, and...
The use of mobile bar code scanners is expanding to markets beyond popular manufacturing uses, such as healthcare, environmental testing and professional services. The successful interaction of users with mobile bar code scanners is of great importance from a business and technology perspective as well as from the user standpoint....
The current proliferation of portable electronic devices for personal
communication, business and entertainment has created a demand for high energy density
power supplies. A hydrocarbon fuel with a conversion efficiency of over
15% can provide greater energy density than current battery technology for these
applications. Current micro-scale heat engines do...
Previous work at Stanford University has demonstrated that inductance in the
substrate connection is the principal problem underlying the coupling of digital
switching noise into analog circuits. The low impedance substrate can be treated
as a single node over a local area. Switching in the digital circuits produces
current transients...
In Radio Frequency Integrated Circuits (RFIC) or high frequency digital
ICs, there is a demand to probe the internal nodes for testing. The ultra low
capacitance RFIC probe presented in his work is a flexible tool for these
applications. The probe utilizes the coupling between a tungsten needle and the...
There is a large and growing market for portable consumer audio products
with very small size. As the size of these products is reduced, the area occupied
by batteries becomes significant and hence limits the number of batteries to one.
In order to build such small products, high levels of...
The objective of this project was to develop an analytical model of a light-framed wood structure using a prevalent structural analysis computer program in order to evaluate system effects and define load paths within the structure, especially under extreme wind events. Simplified modeling techniques and material definitions were developed and...
As more advanced hybrid electric vehicles begin emerging onto the commercial market, design algorithms for their control become increasingly more complicated. One major hurdle for designers is the mitigation and control of the created high frequency harmonics caused from switching the dc voltage into an ac voltage by use of...
This study was to develop and evaluate a shirt pattern for a wheelchair tennis player to improve comfort using reducing garment strain using a CAD program. For that, seven body movements related to garment strain during play were analyzed. In order to develop a pattern, a morphological matrix was used...
The systems currently available for forest road design are not capable of making computer-aided design judgments such as: 1) automated generation of alternative grade lines, 2) optimizing vertical alignment, 3) minimizing total cost of construction, maintenance, and transportation costs, and 4) aiming for least environmental impacts. In recent years, advances...
The purpose of this study was to design and to implement
a practical Ethernet Local Area Network (LAN)
board for the Macintosh II computer system. A survey
of the literature provided a general definition of
LANs, a reference model for network layers, specifications
for an Ethernet LAN, and information on...
In recent years, integrated circuit technology has
spawned the development of many low cost and high performance
microprocessors and microcontrollers. With these devices,
there is an increasing interest in the implementation of
distributed control networks, utilizing microprocessors in the
control nodes.
In this work, a low-cost liquid crystal display (LCD)...
Brushless Doubly Fed Machines (BDFM) have potential advantages in variable
speed generation and adjustable speed drive applications. The most significant of these
advantages is a reduction in the power electronic converter rating, and therefore a
reduction in overall system cost. Presently, efforts are being directed at optimizing the
design of...
A novel method for modeling bends in coplanar waveguides (CPWs) is described. The CPW can be viewed as a pair of parallel coupled quasi-slot lines. Bends in the CPW are modeled as a non-uniform coupled line system in terms of their even- and odd- mode characteristics. This modeling approach is...