VLSI implementation of adaptive BIT/serial IIR filters

Graduate Thesis Or Dissertation

Public Deposited

Citeable URL: https://ir.library.oregonstate.edu/concern/graduate_thesis_or_dissertations/m900nx21v

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Attribute Name	Values
Creator	Badyal, Rajeev
Abstract	A new structure for the implementation of bit/serial adaptive IIR filter is presented. The bit level system consists of gated full adders for the arithmetic unit and data latches for the data path. This approach allows recursive operation of the IIR filter to be implemented without any global interconnections, minimal delay time, chip area and I/O pins. The coefficients of the filter can be updated serially in real time for time invariant and adaptive filtering. A fourth order bit/serial IIR filter is implemented on a 2 micron CMOS technology clocked at 55 MHz.
Resource Type	Masters Thesis
Date Available	2013-01-31T20:19:16+00:00
Date Issued	1992-01-29
Degree Level	Master's
Degree Name	Master of Science (M.S.)
Degree Field	Electrical and Computer Engineering
Degree Grantor	Oregon State University
Commencement Year	1992
Advisor	Kiaei, Sayfe
Academic Affiliation	Electrical and Computer Engineering
Non-Academic Affiliation	Oregon State University. Graduate School
Subject	Electric filters, Digital -- Design and construction Systolic array circuits
Rights Statement	Copyright Not Evaluated
Publisher	Oregon State University
Peer Reviewed	No
Language	English [eng]
Digitization Specifications	File scanned at 300 ppi (Monochrome) using ScandAll PRO 1.8.1 on a Fi-6770A in PDF format. CVista PdfCompressor 5.0 was used for pdf compression and textual OCR.
Replaces	http://hdl.handle.net/1957/36521

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